Eye diagram and jitter: how to read signal integrity

An eye diagram is what a serial link looks like when you fold every bit of it onto the same unit interval. Jitter is the reason the resulting opening has a width at all, rather than a hard edge. At AESTECHNO, an electronic design firm based in Montpellier, we read eye diagrams on every high-speed PCB design we validate, because the eye is the one measurement that turns an abstract loss budget into a pass or a fail.

This article explains both, in the order an engineer actually meets them: how the picture is built, what jitter is made of, why the eye closes, and how we measure it in our lab. The worked example at the end is a PCI Express Gen 3 motherboard whose eye was closed by something that does not resonate anywhere near the data rate: via stubs.

What an eye diagram is, and how it is built

An eye diagram, also called an eye pattern, is a persistence plot in which every unit interval of a serial data stream is overlaid on the same time axis, triggered on the recovered clock. Thousands of bits superimpose into a single picture whose central opening, the eye, shows how much voltage and timing margin the receiver actually has.

The construction matters because it explains what the picture can and cannot tell you. The instrument recovers the clock from the data, slices the waveform into unit intervals and stacks them. Run enough bits and every legal transition is drawn somewhere, so the boundary of the eye is the worst case the link produced during that acquisition.

Two dimensions carry the whole verdict. The vertical opening, the eye height, is the voltage margin left after loss, crosstalk and noise. The horizontal opening, the eye width, is the timing margin left after jitter. A receiver samples somewhere near the centre, so both have to stay open at the sampling instant for the bit to be read correctly.

Contrary to a common assumption, an eye diagram is a statistical picture and not a photograph of a failure. If you capture ten thousand bits you have sampled a probability of error around one in ten thousand, which is eight orders of magnitude away from the 1e-12 bit error rate that PCIe targets. The rare events that actually break links are not in that picture. This is why serious jitter work never stops at the eye and goes on to decomposition and extrapolation, which the next two sections cover.

What jitter is, and the six things it is made of

Jitter is the deviation of a signal edge from where an ideal clock says it should be. It is measured in picoseconds or in fractions of a unit interval, and it is not one phenomenon: it is a sum of components with different statistics, different causes and, most usefully, different fixes.

The first split is the one that governs everything else. Random jitter (RJ) comes from thermal and shot noise, is Gaussian and is unbounded, so it is quoted as an RMS value: quote a peak-to-peak number for it and you have said nothing, because the peak grows with how long you watch. Deterministic jitter (DJ) comes from the circuit and the channel, is bounded, and is quoted peak-to-peak because it has a real maximum.

Deterministic jitter then splits again. Data-dependent jitter (DDJ) tracks the bit pattern and sums inter-symbol interference with duty cycle distortion. Periodic jitter (PJ) comes from a periodic aggressor: a switching regulator, a PLL spur, a coupled clock. Bounded uncorrelated jitter (BUJ) is crosstalk from an unrelated aggressor.

The reason engineers bother with this taxonomy is extrapolation. Because RJ is unbounded, total jitter has no maximum in the abstract, only a maximum at a stated bit error rate. The dual-Dirac model expresses that as TJ = DJ + n x RJ, where n is the number of standard deviations corresponding to the target BER. At a BER of 1e-12 that multiplier is roughly 14.07, counting both sides of the distribution. In our practice this is where most jitter arguments end: a link with modest RJ and large DJ and a link with the reverse can show the same eye at 1e-6 and behave completely differently at 1e-12.

Why the eye closes: loss, reflections and the compliance mask

An eye closes for three separable reasons: the channel attenuates high frequencies more than low ones, discontinuities send energy back down the line, and the receiver must decide inside whatever is left. Each mechanism has its own signature, and telling them apart is most of the diagnostic work.

Frequency-dependent loss is the simplest. Copper and dielectric loss both rise with frequency, so a long trace turns a square edge into a slow one. When the edge has not finished rising before the next bit starts, the residual voltage biases the following bit, which is inter-symbol interference.

Reflections are less intuitive and more damaging. Any impedance discontinuity, a connector, a via, a stub, a footprint pad, sends part of the wave back. That energy returns after a round-trip delay set by the geometry, and if the delay lands near a unit interval it arrives during a later bit. The result is data-dependent jitter that does not scale smoothly with trace length, which is why a short link can fail where a longer one passes. Our stack-up and controlled-impedance methodology keeps this term small.

The compliance mask is the third piece. PCI-SIG, USB-IF and JEDEC each publish a polygon the eye must not touch, defined at a probe point and, from Gen 3 onwards, after a reference equaliser. Despite what the raw picture suggests, a closed eye at the connector is not automatically a failure: Gen 3 and later assume the receiver reopens it with equalisation. The mask, not the eyeball, is the verdict.

Jitter types compared: cause, eye signature, fix

Each jitter component leaves a different mark on the eye and responds to a different intervention. The table below is the working reference we use during bring-up, because it turns "the eye looks bad" into a short list of things worth measuring next.

Read it as a diagnostic path rather than a taxonomy. The signature column is what you look for on the instrument, and the fix column is what actually changes the number. Spending a re-spin on trace length when the dominant term is periodic jitter from a switching regulator is a common and expensive mistake, and we have watched it happen more than once.

The order matters too. Crosstalk is the cheapest hypothesis to test, because quiescing the neighbouring lanes takes minutes and either moves the number or does not. Duty cycle distortion is next, since it shows as two crossings at different heights and needs no decomposition to spot. Only when those are excluded is it worth committing to a layout change in Altium or KiCad, because that is the branch where a re-spin becomes the answer.

One entry deserves emphasis because it is where money gets wasted. The ISI row covers both loss and reflections, and they are not the same problem even though they land in the same bucket. Loss is smooth and predictable and yields to equalisation. Reflections are geometric, they depend on where the discontinuity sits, and equalisation handles them badly. This distinction is the whole subject of the field report below.

How we measure jitter: the bench procedure

Measuring jitter properly means separating the components rather than reporting one number. Our measurement methodology runs the same way on every high-speed interface we validate in 2026, whether it is PCIe, DDR under JEDEC rules, USB, IEEE 802.3 Ethernet or LVDS, because consistency is what makes two boards comparable.

The first step is the clock recovery setting, and it is the step most often got wrong. The standard specifies a recovery bandwidth, and changing it changes the answer: a wider loop tracks more low-frequency wander and reports less jitter. A number quoted without its recovery bandwidth is not a measurement. We set it from the specification, not from the instrument default.

The second step is acquisition depth and pattern. We capture with a compliance pattern where one exists, because data-dependent jitter only appears if the pattern exercises the worst-case run lengths. The third step is decomposition, then extrapolation to the target bit error rate through the bathtub curve. On our Tektronix oscilloscope the TekExpress suite automates the standard-specific parts for PCI Express, USB, DDR, HDMI, Ethernet and MIPI links.

Simulation runs in parallel with the bench, not after it. At AESTECHNO we use ANSYS to simulate signal integrity and power integrity before the first prototype exists, which lets us test a stack-up change or a via change as a numerical experiment rather than a fabrication cycle. We run the signal-integrity solver (ANSYS SIwave for the board level, HFSS where a connector or a via field needs full-wave treatment, with HyperLynx a common alternative in other shops) against the same stack-up the fabricator will build, dimensioned per IPC-2141 transmission-line practice. The correlation between the simulated eye and the measured eye is itself a quality signal: when they disagree, either the model is missing a discontinuity or the board is not what the drawing says.

Decision matrix: re-route, re-spin, re-clock or accept

A marginal eye is a commercial decision as much as a technical one, because the four available responses differ by an order of magnitude in cost and schedule. Our matrix sorts them by which jitter component dominates, since that determines which intervention can work at all.

If deterministic jitter dominates and its source is geometric, a layout change is the only real fix and it is worth the re-spin. If random jitter dominates, no routing work will help and the answer is the clock tree. If periodic jitter dominates, the fix is often cheap and sits in the power domain. If the margin is thin but the dominant term is loss, equalisation settings may buy the whole budget without touching the board.

Unlike the reflex to re-spin, accepting a measured margin is legitimate, but only with a documented number attached. We recommend recording the extrapolated eye opening at the target BER, the measurement temperature and the equaliser settings, so the decision stays auditable. That record is part of the test and validation evidence we hand over at the end of an EVT, DVT and PVT cycle.

Field report: a PCIe Gen 3 eye closed by via stubs

On a recent motherboard project, a board of the class that hosts an Intel or AMD platform, we were called in on a PCI Express Gen 3 link whose eye was closed. The board was manufacturable, the impedance was in tolerance and the routing passed every design rule. The cause turned out to be the part of each via that carried no signal at all: the unused barrel below the exit layer, the stub.

A via drilled through a whole board but exiting on an inner layer leaves the remainder of the barrel hanging as an unterminated transmission line. In our AESTECHNO lab in Montpellier we treat that structure as the first suspect whenever the eye is worse than the loss budget predicts, because it degrades reflections rather than attenuation, and a loss budget does not see it.

Contrary to the common assumption, the stub was not resonating in band. The quarter-wave null of a stub sits at roughly c divided by four times its length times the square root of the dielectric constant. For a 2 mm stub in a laminate around Dk 3.8, that null lands near 19 GHz, while PCIe Gen 3 runs at 8 GT/s with a 125 ps unit interval and a Nyquist frequency of only 4 GHz. Engineers routinely conclude from that arithmetic that stubs are a Gen 5 problem and can be ignored at Gen 3. That conclusion is wrong, and this board was the demonstration.

The mechanism that closed the eye was reflection, not resonance. The stub is a capacitive discontinuity that drops the local impedance, so part of every edge is reflected, travels down the stub, and returns. Even far below the quarter-wave null the reflected energy arrives inside a later bit, which is inter-symbol interference, which is deterministic jitter, which closes the eye horizontally. Our measurement methodology separated the components before anyone touched the layout: the jitter was dominated by the data-dependent term, it tracked the bit pattern, and it did not move when neighbouring lanes were quiesced, which ruled out crosstalk.

The fix is back-drilling: a second, controlled-depth drilling operation from the opposite face that removes the unused barrel. In our practice we specify a residual stub at or below 0.25 mm for anything at 8 GT/s or faster, and, IPC-6012 treats back-drill depth as a qualified board attribute, we require it to appear on the fabrication drawing as a toleranced dimension rather than a note, because a note gets lost between the design file and the panel. Where the layer stack allows it, the cheaper answer is to reassign layers so the signal exits close to the far face and the stub is short by construction. Blind and buried vias solve it too, at an HDI cost premium that is worth checking against the back-drill adder before committing.

The general lesson is the one we now apply on every high-speed design: a loss budget and a set of impedance measurements can both pass while the link fails, because neither of them describes geometry. In our practice, when the measured eye is worse than the simulated one, the difference is almost always a discontinuity the model did not contain, and vertical structures are where we look first.

Bottom line

An eye diagram is the fastest way to see whether a serial link has margin, and jitter is the term that eats the horizontal half of it. Reading the picture is easy. Reading which component closed it is the skill that decides whether you re-route, re-clock or ship, and getting that attribution wrong is what turns a two-week fix into a two-month one.

The through-line of everything above is that an eye is evidence, not a verdict. It is bounded by how long you watched, by the clock-recovery bandwidth you chose and by the equaliser sitting behind the probe point. Change any of those and the same board gives a different answer. Treat the picture as the start of a decomposition rather than the end of a measurement, and the five points below follow from it.

• The eye is a statistical picture, not a photograph. Ten thousand captured bits probe a 1e-4 error rate, eight decades away from the 1e-12 that PCIe requires. Extrapolate through the bathtub curve or you are guessing.
• Random and deterministic jitter are different problems. RJ is unbounded and quoted in RMS, DJ is bounded and quoted peak to peak, and TJ only exists at a stated BER.
• Decompose before you fix. Loss yields to equalisation, reflections do not, and periodic jitter usually lives in the power domain rather than the signal path.
• Stubs close eyes well below their resonance. A 2 mm stub nulls near 19 GHz, yet it closed a Gen 3 link whose Nyquist is 4 GHz, because the mechanism is reflection.
• Put the back-drill depth on the drawing as a toleranced dimension. Specify 0.25 mm or less of residual stub at 8 GT/s and above, and check the HDI alternative against the back-drill adder.

Adjacent reading in this cluster: our guides to stack-up, impedance and EMC compliance, LPDDR4 routing and signal integrity, FPGA board design, RF PCB design, EMC for industrial electronics, industrial video protocols, how a PCB works and the high-performance electronics decision guide. Automotive variants of these links add AEC-Q100 temperature grades on top of the same jitter budget, and EMC pre-compliance to IEC 61000 runs alongside. For slower buses where these effects stay small, such as the ISO 11898 family, see I2C, SPI, UART, I3C and the CAN family. On the industrial side, prototype to series and our design-firm methodology cover what happens after the eye passes, and laminate availability covers what happens when the material you specified is not there.

Written by Hugues Orgitello, who has spent 10+ years designing high-speed electronics at AESTECHNO in Montpellier.

FAQ: eye diagrams and jitter

What is an eye diagram?
An eye diagram is a persistence plot that overlays every unit interval of a serial data stream on the same time axis, triggered on the recovered clock. Thousands of bits superimpose, and the central opening shows the margin the receiver has: the vertical opening is voltage margin left after loss and noise, the horizontal opening is timing margin left after jitter. It is the standard way to judge a high-speed link because it makes the worst case visible in one picture.

What is the difference between random and deterministic jitter?
Random jitter comes from thermal and shot noise, follows a Gaussian distribution and is unbounded, so it is only meaningful as an RMS value. Deterministic jitter comes from the circuit and the channel, has a real maximum, and is quoted peak to peak. The distinction is practical, not academic: total jitter has no value without a stated bit error rate, because the random part keeps growing the longer you watch. The dual-Dirac model combines them as TJ = DJ + n x RJ.

Do via stubs matter at 8 GT/s?
Yes, and the common argument that they do not is based on resonance alone. A 2 mm stub in a Dk 3.8 laminate has its quarter-wave null near 19 GHz, far above the 4 GHz Nyquist frequency of PCIe Gen 3, so the null is genuinely out of band. The stub still acts as a capacitive discontinuity that reflects part of every edge back into the line, and that reflected energy lands inside later bits as inter-symbol interference. We have seen a Gen 3 eye closed by exactly this mechanism.

How much residual stub is acceptable after back-drilling?
For links at 8 GT/s and above we specify 0.25 mm or less of residual stub, and we put the back-drill depth on the fabrication drawing as a toleranced dimension rather than a note. Notes get lost between the design file and the panel. Where the layer assignment allows it, exiting the signal near the far face makes the stub short by construction and costs nothing. Blind and buried vias remove the problem entirely, at an HDI premium worth comparing against the back-drill adder.

How do you convert phase noise into jitter?
Integrate the single-sideband phase-noise curve over the offset band the standard specifies, then convert the integrated phase to time using the carrier frequency. The band matters as much as the curve. According to PCI-SIG, the PCIe Gen 3 reference clock is specified as 1.0 ps RMS integrated from 10 kHz to 50 MHz, whereas the 12 kHz to 20 MHz brick-wall filter that phase-noise analysers apply by default is the Ethernet convention. The same oscillator scores differently under each, so a jitter figure quoted without its integration limits is not comparable to anything. Clock vendors publish both, and the specification tells you which band applies.

Why does my measured eye differ from the simulated one?
Almost always because the model is missing a discontinuity that the board contains. Simulations are usually built from the routing and the stack-up, so they capture loss and impedance well and geometry poorly: via stubs, connector footprints, antipad dimensions and back-drill depth are the usual omissions. The reverse case, a measurement better than the simulation, normally means the model was pessimistic on dielectric loss. In our practice a persistent disagreement is treated as a modelling bug to be found, not a tolerance to be absorbed.