LPDDR4 memory design: routing, signal integrity, power

A 35 mm LPDDR4 byte-lane routed with care typically passes the eye diagram more easily than an 18 mm byte-lane tortured by tight serpentines: in memory routing, discipline matters more than length. Designing embedded products around LPDDR4 and DDR memory is a routine activity at AESTECHNO, and this article shares what we have learned about production-grade LPDDR4 routing: point-to-point topology, DQ/DQS byte-lanes, +/-25 mil length-matching, 40/80 Ohm controlled impedance, and S11 validation below -15 dB.

A product whose memory is poorly routed or undersized immediately feels sluggish, and that sluggishness damages the brand. Mastering DDR routing fundamentals is therefore essential to ship reliable, performant hardware. In this article, we share our experience with the critical aspects of Low-Power Double Data Rate 4 (LPDDR4) design: signal architecture, PCB stack-up, controlled impedance, skew management, and the common pitfalls to avoid.

In a nutshell

What is LPDDR4?

LPDDR4 is the fourth generation of Double Data Rate Random Access Memory (DDR-RAM) in its low-power variant, standardised by JEDEC under the reference JESD209-4. It transfers data at twice the clock rate, with a VDDQ of 1.1 V (0.6 V on the LPDDR4x variant) instead of 1.2 V for standard DDR4, which is why it has become the default choice for embedded and mobile systems according to Micron, Samsung and SK Hynix in their public memory roadmaps.

LPDDR4 routing can look mysterious at first, but it isn't. LPDDR4 is not a variant of DDR4: it is a distinct JEDEC family (JESD209) that shares the DDR-RAM principle. The fundamental difference with standard DDR4 lies in the topology: LPDDR4 uses a point-to-point connection between the SoC and the memory die, whereas DDR4 can run as a bus with one or two DIMMs per channel.

Per the JEDEC JESD209-4 standard (published August 2014), the official reference values every LPDDR4 design starts from:

The Low-Power variant cuts the supply voltage (1.1 V instead of 1.2 V on DDR4, with a VDDQ of 0.6 V on LPDDR4x). In practice, depending on the configuration, the resulting power saving can vary significantly. According to NVIDIA in the design guides of its LPDDR4-based Jetson modules and NXP in its i.MX8 application notes, this is the natural choice for ARM System-on-Chip (SoC) parts such as the NVIDIA Jetson or NXP i.MX8, which embed an LPDDR4 controller compliant with JEDEC JESD209-4 natively.

Routing DDR memory is not just connecting wires. It means understanding the physics: a signal does not travel at the speed of light, but at a fraction of it, set primarily by the dielectric constant of the PCB substrate. That propagation velocity directly drives the skew between signals. You also need to control global and local impedance, because every impedance change generates parasitic reflections.

DDR signal architecture: DQ, DQS and Command/Address groups

DDR signal architecture is built around distinct functional groups (DQ/DQS byte-lanes, Command/Address, differential clock), each with its own length, controlled-impedance (40/80 Ohm) and timing constraints. This grouping, defined by JEDEC JESD209-4, is the first mandatory step in any successful LPDDR4 or DDR4 routing exercise in industrial production.

Three sets of signals make up the interface. The DQ data lines are routed in byte lanes of eight bits, each with its own DQS differential strobe pair and a DM mask; LPDDR4 exposes x16 channels, so every channel is two byte lanes. The Command and Address groups run at half the speed of the DQ groups, which makes them slightly less critical, although skew constraints still apply. Defining these groups in the PCB CAD tool from the start of routing turns skew problem-solving into a methodical exercise.

DQ data groups and DQS strobes

DDR is routed in groups (byte lanes) of single-ended DQ lines, each group timed by its DQS differential pair. The x4 and x8 organisations belong to discrete DDR4 parts (four or eight DQ lines per strobe). LPDDR4 is different: each die exposes x16 channels, usually two per die, so every channel is two byte lanes of eight DQ lines, each with its own DQS pair. That x16 width makes routing harder, because it crowds more constraints (spacing, length) into a smaller PCB area.

Groups are therefore sets of DQs. For a 32-bit memory, we have four groups of 8 DQs (groups 0 to 3). Each group is one byte lane: 8 data bits + 1 DQS strobe pair + a DM mask. We strongly prefer to route every trace of a given group on the same PCB layer, both for skew and for industrial reproducibility.

Role of the DQS strobes

DQS lines are differential strobe signals (80 Ohm differential pair) that act as the local time reference for each group. Their fundamental role is to allow a slightly different length between groups. Instead of having to equalise every DDR signal to the same length (extremely hard given how many there are), it is enough to equalise within each group relative to its DQS strobe. This per-group architecture dramatically simplifies routing.

Command and Address groups

The other groups are the Command and Address (CA) groups. They differ between technologies (LPDDR vs DDR) and according to the internal topology of the memory. One key point: these groups run at half the speed of the DQ groups, which makes their routing slightly less critical, although skew constraints still apply.

It is essential to define these groups in your PCB CAD tool from the very beginning of routing. Good grouping makes skew problem-solving methodical and ensures conformity with the memory vendor's design rules. The challenges here are similar to what we face on PCI Express interfaces, where length-matching of differential pairs is just as critical.

PCB stack-up and material selection

The PCB stack-up is the layered arrangement of conductor and dielectric sheets that make up the printed board, typically 6 to 12 layers for a single-channel LPDDR4 x16 design and up to 28 layers on multi-channel platforms where PCIe and high-speed Ethernet coexist. For an LPDDR4 interface, the stack-up directly drives controlled impedance (40 Ohm single-ended, 80 Ohm differential), trace-to-trace crosstalk, and overall signal integrity. It is a design parameter that must never be left at the foundry default, because it also affects the electromagnetic compatibility (EMC) of the finished product.

The construction of the PCB and its stack-up begins the moment we start the schematic and only really ends when routing is complete. It is an iterative process that converges towards a sweet spot: the trade-off between electrical performance and manufacturing cost. Picking a default stack-up may be acceptable on most products, but on a board carrying DDR4 or LPDDR4 it isn't.

The Master Drawing

Building a PCB is formalised through the Master Drawing. This document gathers every construction detail: layer thicknesses, materials, surface finish, impedance constraints. Industrialising a PCB means making it manufacturable in a real factory, reducing scrap rate while keeping performance close to target. It is a compromise between under-quality and over-quality.

FR-4 versus premium materials

Standard FR-4 is fine for many applications, but for high-speed DDR routing its limits show up quickly: poorly homogeneous dielectric constant, high losses at high frequency, lot-to-lot variation. Premium materials (Rogers, Isola) offer more stable and predictable dielectric properties, at a significantly higher cost. We come back to this cost / performance trade-off in the simulation section.

The stub question

Trace stubs (unterminated trace ends) are still tolerated in DDR4 and LPDDR4, provided they are kept under control. In DDR5 and LPDDR5, however, the data rates are such that stubs become unacceptable and must be eliminated (back-drilling, via-in-pad). We recommend starting to deal with them now, even on LPDDR4, to prepare for the transition to the next generations. For more on high-speed routing techniques, see our dedicated high-speed PCB design guide.

Controlled impedance and reflection management

Controlled impedance is the design discipline that keeps the characteristic impedance stable (40 Ohm single-ended, 80 Ohm differential for LPDDR4) along the full signal path, in order to avoid reflections, losses and timing-margin violations. In LPDDR4 routing, holding that impedance constant is critical to obtain eye diagrams that meet the vendor specification and JEDEC requirements.

Impedance follows from geometry and material, and since the material stays the same along a trace, the work is mostly geometric. The subsections below cover three points: why every impedance discontinuity reflects energy, like an echo in a tunnel; why the nominal trace width computed by the CAD tool is not enough once vias, connectors, neighbouring traces or reference planes alter the local impedance; and why S11, the reflection coefficient, is the number-one criterion for judging constant-impedance routing.

The tunnel-echo analogy

To picture impedance, imagine a tunnel. When you shout into a tunnel, the echo comes back. If your goal is to maximise the sound that reaches the listener at the other end, all that reflected energy is wasted. Worse: if the reflected signal is strong enough, it can disturb the source itself. That is exactly what happens on a PCB trace: every impedance discontinuity generates a reflection that degrades signal integrity.

Global versus local impedance

Impedance is a consequence of geometry and material choice. The material being identical along the full length of a trace, our work is fundamentally a geometric exercise. The nominal trace width is computed by the CAD tool, which is fine on a good package. You still need to understand the calculation algorithm and its limits.

Local impedance is what happens when an impedance-controlled trace finds itself near an element that the nominal calculation ignored: another trace, a connector, a via, a reference plane. A ground via close to a trace will significantly affect local impedance and produce reflections. That is why a visually clean routing can be electrically poor if the immediate environment of the traces was not taken into account.

The S11 parameter: quality criterion number one

We recommend targeting an S11 lower than or equal to -15 dB at the operating frequencies. S11 is the reflection coefficient of your trace: it is the number-one criterion for evaluating the quality of constant-impedance routing. An S11 of -15 dB means that only 3.2 percent of the power is reflected. Above -10 dB, signal-integrity issues become significant.

S11 can be obtained either by parasitic extraction with an electromagnetic simulation tool, or by direct measurement with a vector network analyser (VNA). Mastering electromagnetic compatibility (EMC) is closely tied to these reflection and signal-integrity questions: a poorly matched DDR trace radiates harmonics into the bands monitored by EN 55032 and can compromise certification.

Skew management and length-matching

Skew is the difference in arrival time between two signals that should be synchronous, expressed in picoseconds or in mils of equivalent trace length. According to NXP's i.MX 8M Mini Hardware Developer's Guide (LPDDR4-3000), each DQ/DM must stay within ±10 ps of its DQS (about ±60 mils on FR-4), each DQS within ±85 ps of CK and the CA bus within ±25 ps of CK; targeting ±25 mils inside the byte-lane leaves comfortable margin. JEDEC JESD209-4 describes the memory device (features, AC/DC characteristics, timing) but sets no PCB routing tolerance: those rules come from the SoC vendors' guides. Poor skew control is the most common cause of intermittent failures on high-speed memory interfaces.

Three mechanisms drive the constraint. Setup and hold times define the window during which data must be stable around the clock edge, so every signal in a group must reach the RAM package at the same instant. The DQS strobes, acting as local references, allow a different length between groups, which is what makes routing feasible. The dielectric constant of the PCB material then adds its own skew, even when physical lengths are perfectly equalised.

Setup time and hold time

A signal that arrives early or late will not respect the timing acceptable to the memory. Setup time (time before the clock edge) and hold time (time after the clock edge) define the window during which data must be stable. Because DDR is a parallel bus, every signal in a group must reach the RAM package at the same instant. Vendor datasheets give these values, but we recommend recomputing them systematically on every project.

Intra-group equalisation constraints

Inside a single group (byte lane), trace lengths must be equalised within a typical tolerance of +/-25 mils. The DQS strobes, being local references, allow a different length between groups. It is precisely this architecture that makes routing feasible: without that inter-group flexibility, equalising tens of signals would be near-impossible. TI's SPRAD06C guide (AM62x) says so explicitly: length matching across byte-lanes is "neither required nor recommended".

Effect of the dielectric constant

Signal propagation velocity depends directly on the dielectric constant of the PCB material. Variations in that constant (between layers, between zones of the PCB, or between manufacturing lots) introduce skew even when the physical lengths are perfectly equalised. That is why the maximum acceptable trace length depends more on the PCB material and its construction than on the bare numbers from the memory vendor. Being slightly longer is not catastrophic on a good material with careful routing.

Practical tip: memory placement

At AESTECHNO, we have found that it is often better to place the memory slightly further from the SoC when one is just starting out with DDR routing. It can feel counter-intuitive, but the extra space gives more margin to adjust trace lengths and meet skew constraints. Contrary to the "shorter is better" intuition, we have observed that a 35 mm LPDDR4 byte-lane routed with care typically passes the eye diagram more easily than an 18 mm byte-lane tortured by tight serpentines. On a tightly area-constrained design, close placement requires advanced routing skills, similar to what we encounter on dense embedded systems.

LPDDR4 versus DDR4 versus DDR5: technical comparison

LPDDR4 suits battery-powered and compact embedded designs: 1.1 V core with a 0.6 V I/O rail on LPDDR4x, up to 4266 MT/s on point-to-point 16-bit channels. DDR4 (1.2 V, 3200 MT/s) and DDR5 (1.1 V, 6400 MT/s) suit wider, higher-bandwidth buses at the cost of more routing complexity. The JEDEC figures below settle the choice during the specification phase.

The table compares four generations on data rate per pin, voltage, topology, channel width, stub tolerance and use cases. LPDDR4/4x and LPDDR5 stay point-to-point on 16-bit channels for embedded, mobile and ARM SoC designs. DDR4 keeps a bus topology with one or two DIMMs per channel for servers, PCs and fixed industrial equipment. DDR5 moves to point-to-point 32-bit sub-channels for servers, high-end PCs and AI, and forbids stubs entirely. Read the rows as routing constraints, not only as performance figures.

For a detailed DDR4 versus DDR5 comparison, see our DDR4 vs DDR5 guide, which details the evolution between these two generations and their concrete design implications.

Simulation and validation

Electromagnetic simulation is the method that lets us extract S parameters, eye diagrams and impedance characteristics of a DDR trace before the PCB is even fabricated. It complements VNA and high-bandwidth oscilloscope measurement, the two indispensable pillars to confirm that impedance, skew and timing margins meet the vendor specification before production launch.

The flow combines three steps. Electromagnetic simulation tools (HFSS, CST, HyperLynx, and ANSYS SIwave in our own flow) extract S parameters, check local impedance and simulate eye diagrams before fabrication. Material selection then sets how much margin the simulation has to work with. Finally, eye diagrams and VNA-measured S11 on the real board confirm that timing and voltage margins are sufficient and pinpoint the frequencies that still show reflections.

EM simulation tools

Electromagnetic simulation tools (HFSS, CST, HyperLynx) make it possible to extract S parameters, verify local impedance, and simulate eye diagrams before fabrication. These tools are complex and require sharp expertise. If you do not master them, we recommend calling on a specialist rather than risking misinterpreted results.

Our ANSYS SIwave flow for DDR simulation

At AESTECHNO, we systematically simulate LPDDR4 buses with ANSYS SIwave for Signal Integrity (SI) and Power Integrity (PI). According to Ansys in its DDR-simulation white papers and Cadence in the Sigrity guides, this approach extracts the S parameters of the DQ/DQS byte-lanes, verifies intra-group length-matching, simulates the eye diagram at 4266 Mbps, and analyses the Power Delivery Network (PDN) up to several hundred MHz. Concrete result: we can tell, before fabrication, whether the bus will work, with good accuracy. This capability, rare in the French electronics design market because ANSYS licences are a serious investment, secures the first prototype and avoids costly respins.

Selecting PCB material for LPDDR4

We are experts in selecting the right PCB material for each DDR project. According to Isola in its IS410 datasheets and Panasonic in the Megtron documentation, the dielectric constant Dk and the loss tangent Df vary noticeably between economy FR-4 (Dk approx 4.5, Df approx 0.020 at 1 GHz for an economy grade) and low-loss families such as Megtron. For LPDDR4 at 4266 Mbps, we often favour Isola IS410 or 370HR, high-Tg FR-4 class laminates rather than low-loss ones: stable Dk, low Df dispersion between layers, and a high Tg compatible with multiple Pb-free reflow cycles per the IPC-4101 requirements.

For PCIe Gen5 designs, we step up to Megtron 6/7. We arbitrate Dk, Df, Tg, Coefficient of Thermal Expansion (CTE), thermal stability, fab availability and cost on every specification, including stack-ups up to 28 layers with laser microvias and buried vias.

Eye diagrams and S11 validation

The eye diagram is the graphical representation that summarises the overall quality of a memory link: it captures the combined effect of skew, reflections, crosstalk and attenuation. An open eye means timing and voltage margins are sufficient. The VNA-measured S11 completes that analysis by pinpointing exactly which frequencies show reflections. For more on test and validation methodology, see our high-speed PCB design guide.

The simulation versus material trade-off

Using a cheap material has a hidden cost: you have to compensate with more simulation to validate the design. Premium materials (Rogers, Isola) offer more stable dielectric properties and tolerate routing imperfections better, at a higher fab cost. We find that investment in simulation often allows the material cost to drop by optimising the design to work cleanly on standard FR-4. It is a case-by-case judgement that depends on production volumes and performance constraints.

Common pitfalls and lessons learned

The most damaging DDR-routing pitfall is ignoring the byte-lane groups: the prototype boots on relaxed timing, then fails in series production once process and temperature spread eat the margin. Default stack-ups, unsuitable materials and discontinuous reference planes follow close behind. At AESTECHNO, we have identified several systematic errors that translate into expensive design iterations and time-to-market delays.

The subsections below draw on our multi-generation DDR portfolio, from DDR2 to LPDDR4, and on the eye-diagram audits we run on customer memory buses. They cover why most DDR-routing examples found online deserve caution, why IPC standards such as IPC-2221 are an essential but insufficient base, and the four recurring mistakes we see most often: ignored groups, default stack-ups, unsuitable materials and discontinuous reference planes.

Our DDR expertise: a multi-generation portfolio

At AESTECHNO, the projects we deliver covers the four generations deployed in production: DDR2, DDR3, DDR4 and LPDDR4. That continuity is valuable: the pitfalls that already showed up in DDR3 are amplified in LPDDR4, and a fine-grained understanding of each generation helps anticipate the constraints of the next. We have also audited many customer memory buses through eye-diagram measurement, regularly uncovering signal-integrity defects invisible in nominal operation but critical in series production.

In Q1 2026, we delivered a particularly demanding project around the NVIDIA Jetson Orin NX, with a fully customised Yocto BSP.

Online examples: handle with care

At AESTECHNO, we have observed that the majority of DDR-routing examples available on the web are technically flawed. We strongly advise staying critical. Many of these articles show visually appealing examples, but as you build experience you quickly realise that the routing, while pretty, is in fact pretty poor. Most of the time, those routings ignore the groups. Forgetting that means designing a product that is only good as a prototype. In production, that style of routing will not survive process variation, temperature and component aging for long.

IPC standards: an essential but insufficient base

We remind clients that IPC standards are not mandatory. They exist to simplify communication and align the industry on a shared baseline. As IPC notes in the preamble of IPC-2221 (Generic Standard on Printed Board Design), and as Altera then Xilinx state in their DDR application notes, the industry sometimes runs ahead of the standards on the highest data rates. Be aware of it: applying 100 percent IPC is not always possible nor desirable. Sometimes IPC simply does not define a solution for a specific case.

The very definition of the engineer's job is to make informed compromises. In DDR routing, knowing the IPC documents (IPC-2221, IPC-2226 for HDI, IPC-4101 for materials) is essential. But often, as in any complex routing, you have to step beyond them with technical justification.

Recurring mistakes to avoid

• Groups ignored: the design works on the prototype (ideal conditions) but fails in production (+/-40 degC variations, worst-case components, aging). That is the difference between "it works" and "certifiable".
• Default stack-up: using the PCB fab's standard stack-up without tailoring it to DDR constraints is a common source of impedance issues.
• Unsuitable materials: picking a low-end material without compensating with simulation is playing with fire on a series product.
• Discontinuous reference planes: a trace that crosses to a different reference plane without a stitching via experiences a local impedance break that is hard to detect without simulation.

LPDDR4: a strategic choice for your embedded products

Choosing LPDDR4 is a product-architecture decision that has direct commercial impact, along three core axes: end-user perceived performance, battery life (thanks to the 1.1 V VDDQ, or 0.6 V on LPDDR4x), and the thermal behaviour of the product. At AESTECHNO, we regularly support engineering directors and decision-makers in this memory-sizing exercise as early as the scoping phase.

Each axis has its own subsection below. Bandwidth decides whether video playback, image processing and user interfaces feel smooth or sluggish. Lower power consumption than standard DDR4 extends battery life and reduces the heat to dissipate, which simplifies mechanical design. The choice between LPDDR4, DDR4 and DDR5 then depends on the product: battery-powered or compact designs, fixed industrial equipment, or high-bandwidth and long-life projects. Longevity closes the list, since a poorly anticipated memory choice can force a mid-life redesign.

Performance and user experience

LPDDR4 offers enough bandwidth for most current embedded applications: smooth video playback, image processing, responsive user interfaces. For a product targeting consumer or industrial markets, undersized memory translates immediately into a perception of sluggishness that damages the brand.

Battery life and thermal constraints

LPDDR4 reduces power consumption versus standard DDR4. On a battery-powered product - smartphone, industrial tablet, portable terminal - that gain is a direct competitive advantage. On top of that, lower power means less heat to dissipate, which simplifies mechanical design and reduces throttling risk in constrained environments.

LPDDR4, DDR4 or DDR5: which one for your project?

We have observed that the choice between these technologies depends mainly on the product context:

• LPDDR4/LPDDR4x: battery-powered products, compact embedded, strong thermal constraints. The natural choice for ARM SoCs (such as NVIDIA Jetson, NXP i.MX8).
• DDR4: fixed industrial applications, no battery constraints. Caution: the main DRAM makers announced in 2025 the progressive end of DDR4 production, so check its lifecycle status before choosing it for a long-life product.
• DDR5: projects requiring high bandwidth (AI, multi-stream video processing) or a long product life. See our DDR4 vs DDR5 guide to dig deeper.

Impact on product longevity

LPDDR4 today has solid industrial maturity, with many vendors. For a product with a 5- to 7-year-plus expected lifetime, we recommend checking memory end-of-life roadmaps from the design phase. A poorly anticipated memory choice can trigger an expensive mid-life redesign - see our analysis of electronic-component shortages for the supply-chain side.

LPDDR4 debugging at bring-up: training fails

Unlike slow buses, memory is not debugged by watching wrong bytes go past. At these rates the controller first runs a training sequence, and if that fails there is simply no memory. The bootloader error message is your first instrument.

Training is the sequence in which the controller measures channel delays at start-up, stage by stage: write leveling, read gate training, centring of the write and read data windows, then reference-level adjustment. Each stage can fail separately, and the stage that fails is a diagnosis in itself. The causes, in order of frequency, are controller parameters that do not match the device, insufficient length matching inside a byte lane, misconfigured termination and ODT, power integrity, and the voltage reference. The sections below show how to tell them apart with the tools you already own.

What training does

The controller cannot assume channel delays: they depend on trace length, vias and package. So it measures them at start-up, stage by stage. Write leveling aligns the strobe against the memory clock, compensating the CK-to-DQS skew that trace lengths and packages introduce on each point-to-point channel. Read gate training follows, then centring of the write and read data windows, then reference-level adjustment.

Each stage can fail separately, and the stage that fails is a diagnosis in itself. A write-leveling failure points at clock and strobes, therefore at length matching and topology. A later failure, during centring, points at channel quality or termination.

Causes, in order of frequency

• Controller parameters that do not match the device. Timings, organisation and latencies lifted from an example for a different part number. Most frequent cause and the cheapest to fix.
• Insufficient length matching inside a byte lane. Constraints are tight within a byte, between data and strobe. A local error fails a single lane, which the training result registers often report per byte.
• Termination and ODT misconfigured. Defaults that do not suit the actual topology. The symptom is training that passes at low frequency and fails at the nominal rate.
• Power integrity. Insufficient decoupling network: memory switches a lot of current simultaneously, and local supply collapse shows up as intermittent training failure that differs from boot to boot.
• Voltage reference. VREF badly placed or noisy, shifting the decision threshold and narrowing the usable window.

Telling them apart with what you already own

Read the exact stage that failed rather than the fact of failure. Instrumented bootloaders and controller result registers give the stage and frequently the byte involved. A failure on a single byte lane is a localised routing problem; a failure on all of them is a global clock, supply or parameter problem.

The most informative test costs nothing: lower the memory frequency. If training passes at a reduced rate and fails at nominal, the channel or the termination is responsible, not the logical configuration. If the failure persists at low frequency, look at parameters or a connection error instead.

Finally, training that succeeds is not validation. The reported margins have to be read: centring that passes with a very narrow window will pass on the bench and fail over temperature.

What the mistake costs, and when to call someone

Memory is the subsystem where mistakes cost most, because they are rarely correctable in software. A matching or decoupling defect forces a re-route, therefore a full board iteration. It is also the subsystem where insufficient margin produces the hardest failures to reproduce, correlated with temperature and data pattern.

Reading the training stages and testing at reduced frequency needs nobody, and it frames the problem. What justifies support is the upstream decision: channel simulation before routing, which is the only way to avoid the iteration rather than discover it. See our high-speed design page.

Bottom line

Respecting the byte-lane groups is the first LPDDR4 decision that separates a design that works on the bench from one that survives series production; stack-up, impedance validation and EMC margins come next. Here are the five takeaways we apply on our LPDDR4 / LPDDR4x integrations in our AESTECHNO lab in Montpellier, distilled from a multi-generation DDR portfolio and validated against JEDEC JESD209-4, IPC-2221 and IEEE high-speed-design references.

• Respect the byte-lane groups: keep DQ traces inside +/-25 mils relative to their DQS strobe, route the full byte-lane on a single layer, and never let process variation eat your skew budget.
• Validate impedance early: target S11 below -15 dB across the useful band, cross-check with ANSYS SIwave simulation, and confirm the eye diagrams on our Tektronix scope before sign-off.
• Pick the stack-up before routing: set the layer count and reference planes from the signal-integrity constraints, and Isola IS410 or 370HR, high-Tg FR-4 class laminates per IPC-4101, are our default for DDR/PCIe signals.
• Industrialise with EMC and thermal margins: check EMC margins against EN 55032 and the -40 / +85 degC thermal envelope before greenlighting series.
• Plan for the next generation: route LPDDR4 today with the discipline LPDDR5 will require tomorrow (no stubs, back-drilling, via-in-pad), so the second product generation reuses the design rules without a stack-up rework.

Related articles

• High-speed PCB design and signal integrity - methodology for critical routing
• PCB stack-up, impedance and EMC - controlled-impedance routing fundamentals
• DDR4 versus DDR5 comparison - generational trade-offs and design impact
• NVIDIA Jetson Orin processors - LPDDR4x for embedded AI
• PCI Express bus - high-speed differential routing
• Electronic component shortages - long-term sourcing strategy
• AESTECHNO blog - more articles on embedded electronics and high-speed design

FAQ: LPDDR4 and memory routing

What is the S11 parameter and why target -15 dB?
S11 measures the signal reflection ratio on a trace (reflection coefficient). An S11 of -15 dB means very little energy is reflected and almost all of it is transmitted, which is excellent for signal integrity. An S11 above -10 dB indicates impedance issues with significant reflections. S11 is obtained either by electromagnetic simulation (parasitic extraction) or by measurement with a vector network analyser (VNA). For LPDDR4/DDR4, a good S11 guarantees compliant eye diagrams.

Why are electromagnetic simulations so expensive for DDR interfaces?
EM simulation tools (HFSS, CST, HyperLynx) require costly licences, sharp technical expertise that takes long to build, and significant compute time on complex 3D models. They do, however, allow you to use economical PCB materials by compensating with an optimised design. The alternative is to use premium materials (Rogers, Isola) that tolerate imperfections better but cost significantly more than standard FR-4.

What does "respecting the groups" mean in DDR routing?
In DDR, signals are organised into groups (byte lanes): 8 DQ data bits + 1 DQS strobe pair + DM mask. Every signal in a group must have an equalised length (+/-25 mils) and arrive simultaneously to meet the setup/hold windows. Ignoring the groups can pass a prototype (relaxed timing constraints) but will fail in industrial production (process variation, temperature, aging). It is the difference between "it works" and "certifiable".

Are IPC standards enough for complex DDR routing?
IPC standards provide an essential base (trace widths, spacing, standard stack-ups) but do not cover every advanced case: very high-speed DDR routing (over 3200 MT/s), vendor-specific constraints (process variation), optimisations on non-standard materials. On complex projects, you sometimes have to step beyond IPC with technical justification (simulations, measurements). The engineer's job is to make informed compromises between standards, cost and performance.

Why are so many DDR-routing examples online of poor quality?
Many tutorials show visually correct but technically flawed routings: groups ignored, lengths poorly equalised, discontinuous reference planes, excessive stubs. Such routings can work on prototypes in ideal conditions (stable temperature, sorted components) but fail in production (+/-40 degC variations, worst-case components, aging). For industrial-grade certifiable hardware, follow the SoC and memory vendors' design guides and validate with eye diagrams.