Electronic design house in Montpellier: AESTECHNO methodology

An electronic design house (in French, bureau d'études électronique) is an independent engineering firm that designs, develops and industrializes custom electronic boards for industrial customers. AESTECHNO is one such firm, based in Montpellier, France, serving clients across France and Europe. Our core business is turning a specification into a CE/FCC certified product ready for series production, with hardware design, firmware, EMC and certification handled in-house.

Our electronic design house services

An electronic design house is an engineering firm that designs, develops and industrializes custom electronic boards for industrial customers that lack the internal team or the tools required. At AESTECHNO, our catalogue covers hardware design, firmware, RF, EMC, certification and industrialization, on the same project scope, in the same time zone as you.

• PCB and schematic design (from standard multilayer boards up to 28-layer HDI, laser micro-vias, rigid-flex, integrated antennas). See our PCB design methodology.
• Embedded firmware and real-time software on Zephyr, FreeRTOS, Yocto and embedded Linux. Details in our industrial embedded software guide.
• RF and antenna design up to 10 GHz, RED 2014/53/EU certification. See our RF PCB design page.
• EMC and CE/FCC certification with internal pre-scans before the accredited lab. See our approach to electromagnetic compatibility and CE/RED IoT certification.
• IoT and wireless connectivity: Bluetooth (including 5.4 PAwR), Wi-Fi, LoRaWAN, NB-IoT, LTE-M, 5G. See LPWAN and Bluetooth.
• IoT product cybersecurity aligned with the Cyber Resilience Act and ETSI EN 303 645. See IoT cybersecurity.
• Industrialization and DFM: prototype-to-series transition with a complete file. See DFM and industrialization.

An electronic design house designs electronic boards that are ready to certify and ready to manufacture by orchestrating hardware architecture, electromagnetic compatibility (EMC), real-time firmware and industrialization. At AESTECHNO, based in Montpellier, we apply a 6-step methodology with contractual EVT/DVT/PVT milestones, from the product specification to the pre-series.

The real challenge is not limited to PCB routing: it requires securing EMC (EN 55011 / CISPR 11 Class B, IEC 61000-4-2 ESD ±8 kV contact), BOM longevity (anti-NRND), real-time firmware (FreeRTOS or Zephyr), CE pre-compliance and industrialization in order to deliver a compliant product on schedule. Our product design methodology covers the full cycle, with a risks-first discipline that turns every milestone into a measurable decision point.

In-house pre-compliance instrumentation. Our laboratory features a Tektronix oscilloscope equipped with the TekExpress suite, which runs compliance tests for PCI Express, USB 3.x, MIPI, DDR2 / DDR3 / DDR4, HDMI, Ethernet and LVDS. In practice, we pre-qualify high-speed boards in-house before they reach the accredited lab, which reduces the risk of late non-compliance and accelerates iterations during the DVT phase. This capability sets AESTECHNO apart from most design houses of our size, which subcontract all electrical compliance measurement.

Contents

• Our electronic design house services
• Our 6-step methodology: from spec to pre-series
• EVT/DVT/PVT milestones: contractual commitments
• Sectors and standards
• Transparency on cost categories
• Common pitfalls and field reports
• Example: low-power industrial IoT sensor
• How long does an electronics design project take?
• Bottom line

Our signature know-how: custom industrial projects ready for high-volume production. Most design houses deliver a functional design that will need to be adapted before it can move to series production: EMC fixes after the first lab pass, IPC adjustments at industrialization, DFM handled at the end of the cycle. Our discipline reverses the equation: the product design is the production design. The PCB is designed by the book, EMC pre-compliant, aligned on IPC standards and ready to manufacture at scale as soon as routing is complete. This property is built from the very first line of schematic; it is the difference between a prototype that works and a product that can be industrialized.

Key takeaways

Our 6-step methodology: from spec to pre-series

Designing an electronic board requires a structured process consisting of six steps, from initial scoping to final validation. Each step produces verifiable deliverables and clears a decision gate before moving on, which reduces the technical and financial risk throughout the project.

Step	Phase	Key deliverables	Validation
1. Scoping & architecture	EVT prep	SRS, block diagrams, preliminary BOM	Risk analysis
2. Schematic & BOM	EVT	Verified schematic, long-life BOM (non-NRND), ESD/TVS protections	EMC review
3. PCB routing	EVT	4 to 6-layer PCB, controlled impedances, integrated DfM/DfT	DfX review
4. Prototyping & bring-up	EVT to DVT	Functional prototype, automated tests	Bring-up checklist
5. Embedded firmware	DVT	HAL, drivers, RTOS, OTA, CI/CD pipeline	HIL tests
6. Validation & compliance	DVT to PVT	EMC pre-scan, CE technical file, certification	Accredited lab report

Scoping & architecture

We clarify the SRS (functional requirements, environment, safety, cost/volume, MTBF) and build the complete architecture:

• Power & supply: efficiency, noise, thermal rise, consumption profile.
• Compute: MCU/SoC selection with CPU/RAM headroom and a long-life sourcing channel.
• RF/IoT: BLE, Wi-Fi, LTE-M/NB-IoT, LoRaWAN according to range and energy budget. Our team masters RF PCB design with RED certification, from antenna selection to anechoic chamber qualification.
• Security: secure boot, key management, encrypted OTA. Our approach embeds industrial IoT device cybersecurity from the architecture phase, with continuous validation up to certification.

Deliverables: block diagrams, preliminary BOM, risk analysis (if medical device: ISO 14971).

Schematic & long-life BOM

We select non-NRND references with identified A/B alternates, ESD/TVS protections, galvanic isolation when needed, and we integrate the EMC constraints from this stage: filtering, ground planes, return-current paths. Anticipating component obsolescence and shortages starts at the initial BOM. The result is a robust BOM, available and long-lived.

EMC-driven PCB routing

A 4 to 6-layer stackup is typical, total thickness around 1.6 mm, controlled impedances per IPC-2221: 50 Ω ±10% for single-ended traces, 90 Ω ±10% for USB 2.0, 100 Ω ±10% for differential Ethernet (template defined by the IEEE 802.3 working groups). Differential pairs are routed with skew below 5 mils and a controlled trace-to-plane spacing to preserve signal integrity up to 5 GHz on high-speed buses. Associated DDR memories follow the specifications published by JEDEC (DDR4 JESD79-4, LPDDR4 JESD209-4). For demanding applications, our expertise in high-performance electronic product design relies on ANSYS SI/PI simulations (HFSS, SIwave) to guarantee integrity above the GHz range.

4L vs 6L stackup: how to choose? A 4-layer stackup (signal/GND/PWR/signal) covers most low to mid-frequency IoT products and costs roughly 40% less than a 6-layer board. Above 400 MHz in RF, or for DDR/PCIe buses, the 6-layer stackup (2 buried signal layers between continuous ground planes) becomes nearly unavoidable to hold EMC margins. We arbitrate this choice from scoping, because a respin to add layers typically costs a quarter of delay. The PCB design best practices detail these trade-offs.

DfM (design for manufacturing) and DfT (test) are integrated from the routing stage: access pads, test points spaced at least 2.54 mm apart for bed-of-nails, JTAG/SWD, production connectors. The objective is reliability and testability in series production.

Prototyping & bring-up

Thanks to our PCB and assembly partners in Europe, we produce prototypes quickly. The bring-up follows a methodical checklist: power rails, clocks, memories, communication interfaces. The automated tests cover consumption, thermal performance and RF measurements. We iterate quickly to freeze a stable design before moving to DVT.

Embedded firmware

In parallel with the hardware, we develop the firmware: HAL layer, peripheral drivers, RF communication stacks, RTOS for real-time constraints, signed and rollback-capable OTA via MCUboot. A CI/CD pipeline with unit tests and hardware-in-the-loop catches regressions early in the cycle, with average build times under 5 min for a typical project.

FreeRTOS vs Zephyr: which one to pick? FreeRTOS remains the lightest (kernel footprint under 10 KB, interrupt latency below 1 µs on Cortex-M4), ideal for battery sensors where every byte counts. Zephyr brings a modular architecture, native Bluetooth support and IEC 62443 certifiable security, preferable for connected IoT products targeted by the Cyber Resilience Act. For a deeper dive, see our complete industrial embedded software guide.

Validation & compliance

We prepare CE certification by covering the applicable directives: RED (2014/53/EU), EMC (2014/30/EU), LVD (2014/35/EU), RoHS. The internal EMC pre-scans target the critical limits: EN 55011 Class B (40 dBµV/m at 3 m between 30 and 230 MHz), IEC 61000-4-2 (ESD ±8 kV contact, ±15 kV air), IEC 61000-4-3 (radiated RF immunity 80-1000 MHz at 3 V/m). Depending on the product, we plan HALT (Highly Accelerated Life Test) campaigns in a thermal chamber from -40 °C to +85 °C with vibration up to 50 Grms to validate reliability before production.

For connected IoT products subject to the Cyber Resilience Act (CRA), EU regulation 2024/2847, the harmonized reference standard is ETSI EN 303 645: strong authentication, no default credentials, signed update mechanism. According to ENISA and NIST IR 8259, IoT security must be anchored in the product architecture from the start, not added as a patch. The applicable EMC limits are defined by the International Electrotechnical Commission (IEC) through the IEC 61000 series, while PCB routing requirements rely on IPC-2221 (generic design) and IPC-6012 (performance). Our guide on electromagnetic compatibility details our EMC approach, and our article on CE/RED certification for IoT products explains the regulatory process.

EVT/DVT/PVT milestones: contractual commitments

An EVT/DVT/PVT milestone is a contractual project checkpoint that consists of measurable pass criteria, verifiable deliverables and an explicit client decision right. This approach turns a linear development into a series of controlled steps, each one reducing the remaining project risk.

• EVT (Engineering Validation Test): the prototype is functional, the key functions are validated. Decision to move into DVT.
• DVT (Design Validation Test): the design is stabilized, pre-certifications are performed, the firmware is integrated. Decision to move into PVT.
• PVT (Production Validation Test): the pre-series validates the manufacturing process, the test benches are operational, the product is ready for series production.

We design custom test benches: ICT (In-Circuit Test), functional test, automated scripts with traceability by serial number. The final DfX covers manufacturability, testability and repairability. When required, we prepare a complete PPAP (Production Part Approval Process) file.

To go deeper into the prototype-to-series transition, see our guide on electronic product industrialization and our overview of testing and validation practices for electronic products.

Sectors and standards

A sector standard refers to a body of safety, performance and compliance requirements that applies depending on the domain (medical, automotive, rail). Mastering these references from the design stage avoids costly surprises during certification. We integrate the regulatory requirements into our architecture choices, our PCB routing and our test strategy, for a smooth lab pass.

• Consumer and industrial: CE / RED / EMC / LVD / RoHS. These directives cover the majority of electronic products marketed in Europe.
• Medical: ISO 13485 (quality system), IEC 60601-1 (electrical safety), IEC 62304 (software life cycle), ISO 14971 (risk management). We work with specialized partners for qualification and testing.
• Automotive, rail, aerospace: stricter requirements on EMC, functional safety and traceability.

Our detailed article on CE/RED certification for IoT products explains the process step by step.

Transparency on cost categories

A cost category in an electronics project refers to an identifiable budget line (engineering, prototypes, testing) whose relative weight varies with product complexity. Understanding this structure enables informed decisions on technical trade-offs and identifies optimization levers, without sacrificing quality or regulatory compliance.

• Engineering: architecture, schematic, PCB routing, firmware and tests. This category represents the main share, smoothed across milestones for financial visibility at every step.
• Prototypes: multilayer PCB fabrication, assembly, sourcing of specific components. The number of iterations directly impacts this line.
• Tests and certification: in-house EMC pre-scans (which reduce the risk of failure at the accredited lab), RF tests, LVD. Upstream EMC analysis significantly reduces certification costs.
• AESTECHNO accelerators: our proven libraries (power supplies, MCU, radios), test bench templates and pre-configured CI pipelines reduce development time and the risk of error.

To optimize production cost from the design stage, see our guide on DFM (Design for Manufacturing) in electronics.

Common pitfalls and field reports

An electronics design pitfall refers to a practice that looks correct at scoping but generates respin costs, certification failure or industrialization delay. Below are the pitfalls we encounter regularly and the strategies we have put in place to avoid them, drawn directly from our field experience on a variety of industrial projects.

At AESTECHNO, we have observed that EMC issues discovered late, during the certification phase, drive costly redesigns and significant delays. That is why we run EMC pre-scans from the end of EVT, even before the product reaches the accredited lab. This approach has helped us avoid full respins on many projects. To go deeper, see our guide on electromagnetic compatibility.

In our practice, unanticipated component obsolescence remains a frequent cause of delays in production. We have set up a systematic process to verify the life-cycle status of components (NRND, EOL) and to identify alternates as soon as the BOM is created. Our article on component shortages details this strategy.

We also observe that firmware-hardware integration often holds surprises at the DVT stage when software development was not run in parallel with the hardware. At AESTECHNO, we start the firmware from the EVT phase with hardware-in-the-loop tests, which allows us to detect incompatibilities before they become expensive.

In our practice, we have observed that shortcuts on the PCB stackup (fewer layers, compromised ground planes) are paid for dearly at EMC certification. On a recent project we measured a 4-layer stackup where a 6-layer one was required: result, +8 dB on the 192 MHz harmonic, EN 55011 Class B failure. A correctly sized stackup from the start is an investment that avoids later respins.

Finally, we have learned that a test strategy treated as a late add-on rather than integrated from the design stage complicates industrialization and increases production costs. Integrating test points, JTAG/SWD access and production connectors from the initial routing significantly simplifies the move into series.

Product cybersecurity, according to Thierry Durand (embedded cybersecurity expert at Embedded Expertise), does not boil down to a CVE scan: the real work consists of driving remediation. According to Durand, an embedded project can easily generate 3000+ CVE entries from an SBOM scan, and without a prioritization layer these reports stay unactionable. This view aligns with our CRA approach, where every CI/CD pipeline build produces a CycloneDX SBOM continuously compared against the CVE feed.

Example project: low-power industrial IoT sensor

A low-power industrial IoT sensor is an autonomous battery-powered device, designed for several years of operation without maintenance. Its design mobilizes every skill of our design house: ultra-low-power architecture, long-range communication, deep energy optimization and regulatory compliance.

On a recent project, we designed an autonomous sensor with a target battery life of several years. We selected an ultra-low-power MCU with aggressive sleep modes and fast wake-up. The communication relies on LoRaWAN, chosen for its excellent range/consumption trade-off in industrial environments. We optimized the power supply to minimize standby current: reduced radio duty cycle, peripherals shut down in sleep, current measurement to the microampere.

In our lab, we measured the quiescent current with a Nordic PPK2 paired with a Keithley DMM7510 (7.5 digits) to validate deep-sleep currents to the picoampere. Result: a battery life of 4.7 years measured on a real-world usage profile, and CE compliance validated at the lab after a single round trip, thanks to the upstream EMC pre-scan.

Field report: on a recent client audit, we observed that a poorly controlled return-current path between an analog ground plane and a digital plane had degraded radiated emissions by 15 dB in the 80-120 MHz band. Contrary to the classic "add shielding" answer, we redesigned the return current under the MCU, gaining 12 dB immediately with no additional component.

For similar projects, see our guides on embedded power management and LPWAN technologies (LoRaWAN, NB-IoT, Sigfox).

How long does an electronics design project take?

The duration of an electronics design project is the time between a validated specification and a delivered pre-series, and it depends on product complexity and the number of iterations required. As an indication, a simple IoT sensor (Default class under CRA) is designed in 4 to 6 months from spec to pre-series, with two PCB iterations. An industrial product with RF constraints, strict EMC and RED certification requires 9 to 14 months. A class IIa medical device under IEC 60601-1 and IEC 62304 typically crosses 18 to 24 months due to the documentation requirements of ISO 13485.

In-house vs external design: which trade-off? Contrary to the idea that an internal team always costs less, most electronics SMEs underestimate the full cost: CAD tooling (Altium, HFSS, ANSYS SIwave), simulation subscriptions, EMC pre-scan lab, firmware CI/CD infrastructure. A specialized external design house amortizes those costs across multiple clients and brings the cross-project experience that an internal team cannot reproduce on its own. We recommend evaluating both models on the same project scope before deciding.

Bottom line: what a top-tier electronic design house delivers

A top-tier electronic design house delivers boards that are ready to certify and ready to manufacture from the very first routing iteration, by integrating EMC, BOM longevity, firmware and industrialization as concurrent disciplines rather than sequential ones. At AESTECHNO, we measure this principle concretely: impedances controlled to ±10% (IPC-2221), in-house EMC pre-scan before the accredited lab (CISPR 11/32), FreeRTOS or Zephyr depending on the constraint, MCUboot signed OTA, ETSI EN 303 645 alignment for CRA-targeted products. Our signature fits in one sentence: product design IS production design, with compliance designed in from the schematic, not added at the end of the cycle.

Key points to remember:

• 6-step methodology with contractual EVT/DVT/PVT milestones, no deliverable without a measurable criterion.
• EMC integrated from the schematic, validated by internal pre-scan before the accredited lab (IEC 61000-4-x, CISPR 11/32).
• Long-life BOM (anti-NRND) with A/B alternates identified at schematic capture.
• FreeRTOS or Zephyr firmware + signed MCUboot OTA, ETSI EN 303 645 alignment for the CRA.
• ANSYS SI/PI simulations (HFSS, SIwave) before fabrication: DDR, PCIe and USB 3.x buses are checked virtually before etching.

Related articles

To deepen your knowledge of electronic design and industrialization:

• PCB design: stack-up, impedance, EMC, advanced techniques for routing, stackup and design for manufacturing.
• Industrial embedded software guide, RTOS firmware development with a complete validation methodology.
• Electromagnetic compatibility (EMC), pre-scans and strategies to pass RED/EMC certifications.
• RF PCB design, radio circuits, antennas and RED certification.
• CE/RED certification for IoT products, process and lead times to certify your connected products.
• Design for Manufacturing (DFM), cost-cutting playbook for electronic products.
• Electronic component shortages, BOM strategy and second-source planning.

FAQ: Electronic board design

How many prototyping iterations should I plan for?
Typically two to three iterations depending on the project complexity, especially for EMC and RF. The internal EMC pre-scan run before the accredited lab pass often saves a full iteration. Projects with strict RF constraints (RED) or specific sector standards may require an additional iteration.

Which RTOS should I pick for a connected board?
FreeRTOS and Zephyr are the two most common choices. FreeRTOS offers a mature ecosystem and native integration with many vendor SDKs. Zephyr brings native Bluetooth support, a modular architecture and an active community backed by the Linux Foundation. The choice depends on the required drivers, the security requirements (secure boot, OTA) and the tooling ecosystem of your team.

How can I cut costs in series production?
Series cost optimization starts at the design stage: a DFM approach to reduce assembly steps, components with identified BOM alternates, and fast test benches to lower production cycle time. Standardizing PCB form factors and reducing the number of unique references also helps lower unit costs.

What EMC constraints should I anticipate at design time?
EMC constraints must be integrated from the PCB stackup choice: continuous ground planes, separation of analog and digital zones, supply filtering, and careful routing of high-frequency signals. ESD/TVS protections on external interfaces, decoupling capacitor placement and return-current management are also critical. At AESTECHNO, we run EMC pre-scans to validate these choices before the lab pass.

Can you take over an existing design?
Yes. We carry out a full audit of the existing design covering EMC, security, DfM and testability. After the audit, we draft a prioritized remediation plan and run a targeted respin on the problem areas, without starting from scratch. This approach lets you capitalize on the work already done while fixing the blocking points.