Electronic design services: PCB, firmware, EMC certification

An electronic design company, also called an electronic design house or, in French, a bureau d'études électronique, is an independent engineering firm that designs, develops and industrializes custom electronic boards for industrial customers. AESTECHNO is one such firm, based in Montpellier, France, serving clients across France and Europe. Our core business is turning a specification into a CE/FCC certified product ready for series production, with hardware design, firmware, EMC and certification handled in-house.

Our electronic design services

Electronic design services cover the whole path from a product idea to a manufacturable board: system architecture, schematic capture, PCB layout, embedded firmware, RF, EMC and the certification file. An electronic design company is the engineering firm that runs that path for industrial customers who lack the internal team or the tools required.

At AESTECHNO, our catalog covers hardware design, firmware, RF, EMC, certification and industrialization on the same project scope, under one roof. One technical point of contact carries the whole scope, with no cascaded subcontracting, from blank page to production transfer and volume manufacturing support.

Seven service families structure the offer, from PCBs up to 28-layer HDI and firmware on Zephyr, FreeRTOS or Yocto through to RF up to 10 GHz, EMC pre-scans run in house, IoT connectivity from Bluetooth 5.4 to NB-IoT, CRA-aligned cybersecurity and DFM industrialization:

• PCB and schematic design (from standard multilayer boards up to 28-layer HDI, laser micro-vias, rigid-flex, integrated antennas). See our PCB design methodology.
• Embedded firmware and real-time software on Zephyr, FreeRTOS, Yocto and embedded Linux. Details in our industrial embedded software guide.
• RF and antenna design up to 10 GHz, RED 2014/53/EU certification. See our RF PCB design page.
• EMC and CE/FCC certification with internal pre-scans before the accredited lab. See our approach to electromagnetic compatibility and CE/RED IoT certification.
• IoT and wireless connectivity: Bluetooth (including 5.4 PAwR), Wi-Fi, LoRaWAN, NB-IoT, LTE-M, 5G. See LPWAN and Bluetooth.
• IoT product cybersecurity aligned with the Cyber Resilience Act and ETSI EN 303 645. See IoT cybersecurity.
• Industrialization and DFM: prototype-to-series transition with a complete file. See DFM and industrialization.

An electronic design company designs electronic boards that are ready to certify and ready to manufacture by orchestrating hardware architecture, electromagnetic compatibility (EMC), real-time firmware and industrialization. At AESTECHNO, based in Montpellier, we apply a 6-step methodology with contractual EVT/DVT/PVT milestones, from the product specification to the pre-series.

The real challenge is not limited to PCB routing: it requires securing EMC (EN 55011 / CISPR 11 Class B, IEC 61000-4-2 ESD ±8 kV contact), BOM longevity (anti-NRND), real-time firmware (FreeRTOS or Zephyr), CE pre-compliance and industrialization in order to deliver a compliant product on schedule. Our product design methodology covers the full cycle, with a risks-first discipline that turns every milestone into a measurable decision point.

In-house pre-compliance instrumentation. Our laboratory features a Tektronix oscilloscope equipped with the TekExpress suite, which runs compliance tests for PCI Express, USB 3.x, MIPI, DDR2 / DDR3 / DDR4, HDMI, Ethernet and LVDS. In practice, we pre-qualify high-speed boards in-house before they reach the accredited lab, which reduces the risk of late non-compliance and accelerates iterations during the DVT phase. This capability sets AESTECHNO apart from most electronics design firms of our size, which subcontract all electrical compliance measurement.

Contents

• Our electronic design services
• Our 6-step methodology: from spec to pre-series
• EVT/DVT/PVT milestones: contractual commitments
• Our engagement model: fixed price on the deliverable
• Sectors and standards
• Where we work
• Who holds which certification, and why it matters
• Transparency on cost categories
• Common pitfalls and field reports
• Example: low-power industrial IoT sensor
• How long does an electronics design project take?
• Bottom line

Our signature know-how: custom industrial projects ready for high-volume production. Most design firms deliver a functional design that will need to be adapted before it can move to series production: EMC fixes after the first lab pass, IPC adjustments at industrialization, DFM handled at the end of the cycle. Our discipline reverses the equation: the product design is the production design. The PCB is designed by the book, EMC pre-compliant, aligned on IPC standards and ready to manufacture at scale as soon as routing is complete. This property is built from the very first line of schematic; it is the difference between a prototype that works and a product that can be industrialized.

To see the classes of project we run (radar, lidar, SDR, embedded Linux compute, 10 kV power, IoT sensors), browse our work.

Key takeaways

Our 6-step methodology: from spec to pre-series

Designing an electronic board requires a structured process consisting of six steps, from initial scoping to final validation. Each step produces verifiable deliverables and clears a decision gate before moving on, which reduces the technical and financial risk throughout the project. The six steps run from scoping and architecture to compliance validation, through schematic capture with a durable BOM, EMC-driven PCB routing, prototyping with methodical bring-up, and embedded firmware. Three contractual milestones, EVT, DVT and PVT, punctuate the path and give the customer a measurable decision right before committing to the next phase, so the scope stays auditable at every gate. Each gate produces a written go or no-go, with evidence attached.

Scoping & architecture

We clarify the SRS (functional requirements, environment, safety, cost/volume, MTBF) and build the complete architecture:

• Power & supply: efficiency, noise, thermal rise, consumption profile.
• Compute: MCU/SoC selection with CPU/RAM headroom and a long-life sourcing channel.
• RF/IoT: BLE, Wi-Fi, LTE-M/NB-IoT, LoRaWAN according to range and energy budget. Our team masters RF PCB design with RED certification, from antenna selection to anechoic chamber qualification.
• Security: secure boot, key management, encrypted OTA. Our approach embeds industrial IoT device cybersecurity from the architecture phase, with continuous validation up to certification.

Deliverables: block diagrams, preliminary BOM, risk analysis (if medical device: ISO 14971).

Schematic & long-life BOM

We select non-NRND references with identified A/B alternates, ESD/TVS protections, galvanic isolation when needed, and we integrate the EMC constraints from this stage: filtering, ground planes, return-current paths. Anticipating component obsolescence and shortages starts at the initial BOM. The result is a robust BOM, available and long-lived.

EMC-driven PCB routing

A 4 to 6-layer stackup is typical, total thickness around 1.6 mm, controlled impedances per IPC-2221: 50 Ω ±10% for single-ended traces, 90 Ω ±10% for USB 2.0, 100 Ω ±10% for differential Ethernet (template defined by the IEEE 802.3 working groups). Differential pairs are routed with skew below 5 mils and a controlled trace-to-plane spacing to preserve signal integrity up to 5 GHz on high-speed buses. Associated DDR memories follow the specifications published by JEDEC (DDR4 JESD79-4, LPDDR4 JESD209-4). For demanding applications, our expertise in high-performance electronic product design relies on ANSYS SI/PI simulations (HFSS, SIwave) to guarantee integrity above the GHz range.

4L vs 6L stackup: how to choose? A 4-layer stackup (signal/GND/PWR/signal) covers most low to mid-frequency IoT products and costs roughly 40% less than a 6-layer board. Above 400 MHz in RF, or for DDR/PCIe buses, the 6-layer stackup (2 buried signal layers between continuous ground planes) becomes nearly unavoidable to hold EMC margins. We arbitrate this choice from scoping, because a respin to add layers typically costs a quarter of delay. The PCB design best practices detail these trade-offs.

DfM (design for manufacturing) and DfT (test) are integrated from the routing stage: access pads, test points spaced at least 2.54 mm apart for bed-of-nails, JTAG/SWD, production connectors. The objective is reliability and testability in series production.

Prototyping & bring-up

Thanks to our PCB and assembly partners in Europe, we produce prototypes quickly. The bring-up follows a methodical checklist: power rails, clocks, memories, communication interfaces. The automated tests cover consumption, thermal performance and RF measurements. We iterate quickly to freeze a stable design before moving to DVT.

Embedded firmware

In parallel with the hardware, we develop the firmware: HAL layer, peripheral drivers, RF communication stacks, RTOS for real-time constraints, signed and rollback-capable OTA via MCUboot. A CI/CD pipeline with unit tests and hardware-in-the-loop catches regressions early in the cycle, with average build times under 5 min for a typical project.

FreeRTOS vs Zephyr: which one to pick? FreeRTOS remains the lightest (kernel footprint under 10 KB, interrupt latency below 1 µs on Cortex-M4), ideal for battery sensors where every byte counts. Zephyr brings a modular architecture, native Bluetooth support and IEC 62443 certifiable security, preferable for connected IoT products targeted by the Cyber Resilience Act. For a deeper dive, see our complete industrial embedded software guide.

Validation & compliance

We prepare CE certification by covering the applicable directives: RED (2014/53/EU), EMC (2014/30/EU), LVD (2014/35/EU), RoHS. The internal EMC pre-scans target the critical limits: EN 55011 Class B (40 dBµV/m at 3 m between 30 and 230 MHz), IEC 61000-4-2 (ESD ±8 kV contact, ±15 kV air), IEC 61000-4-3 (radiated RF immunity 80-1000 MHz at 3 V/m). Depending on the product, we plan HALT (Highly Accelerated Life Test) campaigns in a thermal chamber from -40 °C to +85 °C with vibration up to 50 Grms to validate reliability before production.

For connected IoT products subject to the Cyber Resilience Act (CRA), EU regulation 2024/2847, the harmonized reference standard is ETSI EN 303 645: strong authentication, no default credentials, signed update mechanism. According to ENISA and NIST IR 8259, IoT security must be anchored in the product architecture from the start, not added as a patch. The applicable EMC limits are defined by the International Electrotechnical Commission (IEC) through the IEC 61000 series, while PCB routing requirements rely on IPC-2221 (generic design) and IPC-6012 (performance). Our guide on electromagnetic compatibility details our EMC approach, and our article on CE/RED certification for IoT products explains the regulatory process.

EVT/DVT/PVT milestones: contractual commitments

An EVT/DVT/PVT milestone is a contractual project checkpoint that consists of measurable pass criteria, verifiable deliverables and an explicit client decision right. This approach turns a linear development into a series of controlled steps, each one reducing the remaining project risk. EVT (Engineering Validation Test) freezes the architecture and the design, DVT (Design Validation Test) validates the product against its requirements, its environment and its EMC pre-compliance, and PVT (Production Validation Test) qualifies the production tooling and its repeatability. At each milestone the pass criteria are written into the contract rather than left to judgment on the day: that is what keeps project risk steerable, step by step, for both sides of the contract.

• EVT (Engineering Validation Test): the prototype is functional, the key functions are validated. Decision to move into DVT.
• DVT (Design Validation Test): the design is stabilized, pre-certifications are performed, the firmware is integrated. Decision to move into PVT.
• PVT (Production Validation Test): the pre-series validates the manufacturing process, the test benches are operational, the product is ready for series production.

We design custom test benches: ICT (In-Circuit Test), functional test, automated scripts with traceability by serial number. The final DfX covers manufacturability, testability and repairability. When required, we prepare a complete PPAP (Production Part Approval Process) file.

To go deeper into the prototype-to-series transition, see our guide on electronic product industrialization and our overview of testing and validation practices for electronic products.

Our engagement model: fixed price on the deliverable

Our engagement model is a fixed price on the deliverable rather than an hourly rate on effort. We contract on the delivery of a pre-production optimized working prototype on the first attempt, at a price agreed before the work starts, so the budget is a number you approve up front instead of a running total you discover at the end.

American buyers are usually offered three models by name: Fixed Price, Time and materials (T&M) and a dedicated team. We name ours the same way, because a supplier that will not name its model is asking you to guess. AESTECHNO contracts on the result, not on the hours spent reaching it: scope, acceptance criteria and price are settled before the first schematic sheet is opened, and the milestone the money hangs on is a prototype that works.

A fixed price against a written scope is not padding. Against an unscoped project it is, and it has to be. That is the precondition most suppliers leave unsaid: a fixed price needs a written scope before the work starts. A project nobody has scoped yet can't honestly be quoted at a fixed price, and a supplier who quotes one anyway recovers the difference in change orders.

T&M is not the weaker choice either. On real exploration (does this architecture hold, which of two radio chains wins, what is actually causing an uncharacterized EMC failure) a fixed price forces someone to put a number on an unknown, which means padding it. On bounded exploration, T&M costs you less and lets you stop the moment the answer arrives. Unbounded, it is the model that runs away from you, which is the whole historical case for fixed price.

Where we stand. We work fixed price on an engagement to deliver, not on hours. The scope is written at the end of a short scoping phase, and a change of scope goes through a priced change order rather than a quiet drift in the budget.

That commitment is only defensible because of the engineering discipline behind it. Signal and power integrity are simulated in ANSYS HFSS and SIwave before the board is fabricated, EMC is designed in from the schematic and pre-scanned in our own lab before the accredited lab sees the product, and every gate closes on written pass criteria. American teams usually name the hardware ladder MVP, EVT, DVT, PVT; our contractual milestones are the last three, and the first working build is the one the fixed price is attached to. Across the 65 projects delivered since 2022, every product we took to certification passed CE/FCC at the first attempt.

Where a fixed price would not be honest, we say so rather than pricing an unknown. An exploratory feasibility study, a rescue on a design somebody else started, or a specification that is still moving all deserve a short scoped phase first, at the end of which a fixed price actually means something. The contract carries the commitment; this page only describes how we work.

Sectors and standards

A sector standard refers to a body of safety, performance and compliance requirements that applies depending on the domain (medical, automotive, rail). Mastering these references from the design stage avoids costly surprises during certification. We integrate the regulatory requirements into our architecture choices, our PCB routing and our test strategy, for a smooth lab pass. Depending on the sector, that covers IEC 60601-1 and IEC 62304 for medical together with ISO 13485 and ISO 14971, industrial EMC per CISPR 11/32 and IEC 61000-4-x, the RED 2014/53/EU directive for radio, and the Cyber Resilience Act with ETSI EN 303 645 for connected products. The applicable framework is identified at scoping, never discovered during certification.

• Consumer and industrial: CE / RED / EMC / LVD / RoHS. These directives cover the majority of electronic products marketed in Europe.
• Medical: ISO 13485 (quality system), IEC 60601-1 (electrical safety), IEC 62304 (software life cycle), ISO 14971 (risk management). We work with specialized partners for qualification and testing.
• Automotive and rail: stricter requirements on EMC, functional safety and traceability.
• Vision and AI compute: NVIDIA Jetson Orin NX carrier boards with a custom Yocto BSP, MIPI-CSI camera integration, and industrialization support for high-power AI silicon.

Our detailed article on CE/RED certification for IoT products explains the process step by step.

Where we work

Electronic design is delivered remotely. Schematics, routing, design reviews, firmware and certification files move over video calls and file exchange, so physical proximity is not a selection criterion for an electronics design firm, unlike an installer or a maintenance provider.

We work from Grabels, in the Montpellier metropolitan area, with industrial clients spread across France: in Occitanie (Toulouse, Nîmes), in Franche-Comté and in the Hauts-de-France. Travel is reserved for the moments that justify it: kickoff meetings, critical design reviews, bench bring-up and EMC campaigns at an accredited lab. The rest of a project does not depend on distance.

Europe and North America are equally part of the markets we take work in. At that range the question stops being geographic and becomes regulatory: CE marking and the RED directive on one side, FCC authorization on the other, with different test campaigns and different files. We cover that gap in our guide to what hardware and firmware design services cost, which also carries the third-party lab ranges for a CE, RED and FCC campaign.

Who holds which certification, and why it matters

Buyers searching for a "certified electronics manufacturer" are usually looking for one supplier holding every certificate. That supplier does not really exist, because design competence and production quality are certified by different schemes, awarded to different kinds of organization.

On the design side, our designer is IPC CID+ certified (Advanced Certified Interconnect Designer). It is not a self-declaration: the plain CID is a mandatory prerequisite, and the CID+ examination covers fabrication materials, electrical and signalling issues, complex component mounting strategies and high-end design. It is awarded by IPC, the body that publishes the IPC-2221 and IPC-6012 standards our layouts are built against, and it does not expire.

On the production side, we work with ISO 13485-certified manufacturing partners. ISO 13485 certifies a quality-management system, and the scope of that certificate varies: it can cover design (clause 7.3 of the standard), manufacturing, or both. A design company can therefore hold it on a design scope, and a contract manufacturer on a production scope. The useful question to ask a supplier is not "are you ISO 13485 certified?" but "what exactly does your certificate cover?".

For our part, we do not hold an ISO 13485 certificate: we design to the standard and to ISO 14971 for risk analysis, and manufacturing goes to certified partners. What we have to demonstrate is design competence and the ability to produce a traceable, auditable design file.

What a design firm must demonstrate instead is design competence and the ability to produce a compliant, auditable design file: traceable requirements, risk analysis aligned with ISO 14971, and a manufacturing package a certified workshop can build without reinterpreting it. That is the link we hold, and we manage the handover to the second one.

Transparency on cost categories

A cost category in an electronics project refers to an identifiable budget line (engineering, prototypes, testing) whose relative weight varies with product complexity. Understanding this structure enables informed decisions on technical trade-offs and identifies optimization levers, without sacrificing quality or regulatory compliance. Five categories dominate the structure: design engineering, prototype iterations, testing and EMC pre-compliance, accredited-lab certification, and industrialization with its test benches. Their relative weight is steered from the architecture stage: that is where the PCB layer count, the selected components and the certification scope for each target market are decided. Steering them early keeps the budget an engineering variable rather than a surprise, whether the product is a simple sensor or a computing board.

• Engineering: architecture, schematic, PCB routing, firmware and tests. This category represents the main share, smoothed across milestones for financial visibility at every step.
• Prototypes: multilayer PCB fabrication, assembly, sourcing of specific components. The number of iterations directly impacts this line.
• Tests and certification: in-house EMC pre-scans (which reduce the risk of failure at the accredited lab), RF tests, LVD. Upstream EMC analysis significantly reduces certification costs.
• AESTECHNO accelerators: our proven libraries (power supplies, MCU, radios), test bench templates and pre-configured CI pipelines reduce development time and the risk of error.

To optimize production cost from the design stage, see our guide on DFM (Design for Manufacturing) in electronics.

Common pitfalls and field reports

An electronics design pitfall refers to a practice that looks correct at scoping but generates respin costs, certification failure or industrialization delay. Below are the pitfalls we encounter regularly and the strategies we have put in place to avoid them, drawn directly from our field experience on a variety of industrial projects.

At AESTECHNO, we have observed that EMC issues discovered late, during the certification phase, drive costly redesigns and significant delays. That is why we run EMC pre-scans from the end of EVT, even before the product reaches the accredited lab. This approach has helped us avoid full respins on many projects. To go deeper, see our guide on electromagnetic compatibility.

In our practice, unanticipated component obsolescence remains a frequent cause of delays in production. We have set up a systematic process to verify the life-cycle status of components (NRND, EOL) and to identify alternates as soon as the BOM is created. Our article on component shortages details this strategy.

We also observe that firmware-hardware integration often holds surprises at the DVT stage when software development was not run in parallel with the hardware. At AESTECHNO, we start the firmware from the EVT phase with hardware-in-the-loop tests, which allows us to detect incompatibilities before they become expensive.

In our practice, we have observed that shortcuts on the PCB stackup (fewer layers, compromised ground planes) are paid for dearly at EMC certification. On a recent project we measured a 4-layer stackup where a 6-layer one was required: result, +8 dB on the 192 MHz harmonic, EN 55011 Class B failure. A correctly sized stackup from the start is an investment that avoids later respins.

Finally, we have learned that a test strategy treated as a late add-on rather than integrated from the design stage complicates industrialization and increases production costs. Integrating test points, JTAG/SWD access and production connectors from the initial routing significantly simplifies the move into series.

Product cybersecurity, according to Thierry Durand (embedded cybersecurity expert at Embedded Expertise), does not boil down to a CVE scan: the real work consists of driving remediation. According to Durand, an embedded project can easily generate 3000+ CVE entries from an SBOM scan, and without a prioritization layer these reports stay unactionable. This view aligns with our CRA approach, where every CI/CD pipeline build produces a CycloneDX SBOM continuously compared against the CVE feed.

Example project: low-power industrial IoT sensor

A low-power industrial IoT sensor is an autonomous battery-powered device, designed for several years of operation without maintenance. Its design mobilizes every skill of our engineering team: ultra-low-power architecture, long-range communication, deep energy optimization and regulatory compliance.

On a recent project, we designed an autonomous sensor with a target battery life of several years. We selected an ultra-low-power MCU with aggressive sleep modes and fast wake-up. The communication relies on LoRaWAN, chosen for its excellent range/consumption trade-off in industrial environments. We optimized the power supply to minimize standby current: reduced radio duty cycle, peripherals shut down in sleep, current measurement to the microampere.

In our lab, we measured the quiescent current with a Nordic PPK2 paired with a Keithley DMM7510 (7.5 digits) to validate deep-sleep currents to the picoampere. Result: a battery life of 4.7 years measured on a real-world usage profile, and CE compliance validated at the lab after a single round trip, thanks to the upstream EMC pre-scan.

Field report: on a recent client audit, we observed that a poorly controlled return-current path between an analog ground plane and a digital plane had degraded radiated emissions by 15 dB in the 80-120 MHz band. Contrary to the classic "add shielding" answer, we redesigned the return current under the MCU, gaining 12 dB immediately with no additional component.

For similar projects, see our guides on embedded power management and LPWAN technologies (LoRaWAN, NB-IoT, Sigfox).

How long does an electronics design project take?

The duration of an electronics design project is the time between a validated specification and a delivered pre-series, and it depends on product complexity and the number of iterations required. As an indication, a simple IoT sensor (Default class under CRA) is designed in 4 to 6 months from spec to pre-series, with two PCB iterations. An industrial product with RF constraints, strict EMC and RED certification requires 9 to 14 months. A class IIa medical device under IEC 60601-1 and IEC 62304 typically crosses 18 to 24 months due to the documentation requirements of ISO 13485.

In-house vs external design: which trade-off? Contrary to the idea that an internal team always costs less, most electronics SMEs underestimate the full cost: CAD tooling (Altium, HFSS, ANSYS SIwave), simulation subscriptions, EMC pre-scan lab, firmware CI/CD infrastructure. A specialized outside design firm amortizes those costs across multiple clients and brings the cross-project experience that an internal team cannot reproduce on its own. We recommend evaluating both models on the same project scope before deciding.

Bottom line: what a top-tier electronic design company delivers

A top-tier electronic design company delivers boards that are ready to certify and ready to manufacture from the very first routing iteration, by integrating EMC, BOM longevity, firmware and industrialization as concurrent disciplines rather than sequential ones. At AESTECHNO, we measure this principle concretely: impedances controlled to ±10% (IPC-2221), in-house EMC pre-scan before the accredited lab (CISPR 11/32), FreeRTOS or Zephyr depending on the constraint, MCUboot signed OTA, ETSI EN 303 645 alignment for CRA-targeted products. Our signature fits in one sentence: product design IS production design, with compliance designed in from the schematic, not added at the end of the cycle.

Key points to remember:

• 6-step methodology with contractual EVT/DVT/PVT milestones, no deliverable without a measurable criterion.
• EMC integrated from the schematic, validated by internal pre-scan before the accredited lab (IEC 61000-4-x, CISPR 11/32).
• Long-life BOM (anti-NRND) with A/B alternates identified at schematic capture.
• FreeRTOS or Zephyr firmware + signed MCUboot OTA, ETSI EN 303 645 alignment for the CRA.
• ANSYS SI/PI simulations (HFSS, SIwave) before fabrication: DDR, PCIe and USB 3.x buses are checked virtually before etching.

Related articles

To deepen your knowledge of electronic design and industrialization:

• High-performance electronics project: a decision-maker's guide (simulation before fabrication, 7 questions to ask).
• PCB design: stack-up, impedance, EMC, advanced techniques for routing, stackup and design for manufacturing.
• Industrial embedded software guide, RTOS firmware development with a complete validation methodology.
• Electromagnetic compatibility (EMC), pre-scans and strategies to pass RED/EMC certifications.
• RF PCB design, radio circuits, antennas and RED certification.
• CE/RED certification for IoT products, process and lead times to certify your connected products.
• Design for Manufacturing (DFM), cost-cutting playbook for electronic products.
• Electronic component shortages, BOM strategy and second-source planning.

FAQ: Electronic board design

How many prototyping iterations should I plan for?
Typically two to three iterations depending on the project complexity, especially for EMC and RF. The internal EMC pre-scan run before the accredited lab pass often saves a full iteration. Projects with strict RF constraints (RED) or specific sector standards may require an additional iteration.

Which RTOS should I pick for a connected board?
FreeRTOS and Zephyr are the two most common choices. FreeRTOS offers a mature ecosystem and native integration with many vendor SDKs. Zephyr brings native Bluetooth support, a modular architecture and an active community backed by the Linux Foundation. The choice depends on the required drivers, the security requirements (secure boot, OTA) and the tooling ecosystem of your team.

How can I cut costs in series production?
Series cost optimization starts at the design stage: a DFM approach to reduce assembly steps, components with identified BOM alternates, and fast test benches to lower production cycle time. Standardizing PCB form factors and reducing the number of unique references also helps lower unit costs.

What EMC constraints should I anticipate at design time?
EMC constraints must be integrated from the PCB stackup choice: continuous ground planes, separation of analog and digital zones, supply filtering, and careful routing of high-frequency signals. ESD/TVS protections on external interfaces, decoupling capacitor placement and return-current management are also critical. At AESTECHNO, we run EMC pre-scans to validate these choices before the lab pass.

Can you take over an existing design?
Yes. We carry out a full audit of the existing design covering EMC, security, DfM and testability. After the audit, we draft a prioritized remediation plan and run a targeted respin on the problem areas, without starting from scratch. This approach lets you capitalize on the work already done while fixing the blocking points.

Buyer questions we get asked before signing

What do I get when the project is finished?
The complete design package: schematic and PCB source files in their native CAD format, Gerber and drill files, assembly drawings and pick-and-place data, the bill of materials with its qualified alternates, firmware sources and build scripts, the bring-up and test procedures, the production test-bench definition, and the CE technical file with the pre-scan and accredited-lab reports. The test that matters is simple: a contract manufacturer should be able to build the product from that package without calling us.

Can you guarantee the quality of the product?
We contract on the deliverable rather than on hours, and the commitment is a pre-production optimized working prototype on the first attempt for a fixed price agreed up front. The contract carries that commitment, not a slogan on a web page. The evidence behind it is public where it can be: every product we have taken to certification passed CE/FCC at the first attempt, and a custom COM Express carrier board we designed has been shipping in the thousands of units per year for three years with no manufacturing-driven redesign and no support call back to us.

My device needs CE and FCC certification. Can you help me comply with it?
Yes, and we design for it from the schematic instead of testing for it at the end. On the European side we cover the RED 2014/53/EU, EMC 2014/30/EU and Low Voltage 2014/35/EU directives plus RoHS, assemble the technical file and run the EMC pre-scan in our own lab before the accredited lab. On the US side we prepare the FCC Part 15 route in the same campaign, which costs on the order of 20 to 30 percent more than CE and RED alone because the test set is nearly the same. One caution: a pre-certified radio module does not certify your product. The finished device still needs its own EMC testing.

Can you estimate the cost of the final device before it's built?
Yes, for the unit cost of the device itself, which is usually the number that decides whether the product has a business case. We build a preliminary bill of materials at the architecture stage and price it at your target volume, then add the bare PCB (layer count, technology class, panel yield), assembly complexity, enclosure and the test time per unit. It starts as a range and narrows at each gate as the BOM freezes.

What we will not do is put a device cost on a product whose architecture does not exist yet, because one layer of stack-up or one radio choice moves that number more than any negotiation will.

Who are your customers?
Industrial, medical and connected-product companies, from startups to established manufacturers: 59 clients and 65 projects delivered since we were founded in 2022. They sit across France and the rest of Europe, and the United States is a market we serve. Most engagements are covered by an NDA, so we describe classes of project rather than names: radar, lidar, SDR, embedded Linux compute, high-voltage power supplies, low-power IoT sensors.