PCB design guide: stack-up, impedance and EMC compliance

A well-designed PCB (Printed Circuit Board) imposes its own specifications: controlled impedances within ±10% per IPC-2221, symmetrical stack-up, continuous ground planes, IPC-7351 footprints and finishes compliant with IPC-A-600. At AESTECHNO, an electronic design house based in Montpellier, we have been designing PCBs from 2 to 28 layers (rigid, flex and HDI) for over 10 years, with one guiding discipline: the PCB is a component, not a substrate.

Industrial fabrication qualification is governed, according to the Association Connecting Electronics Industries (the IPC), by IPC-6012; assembly acceptability is defined, per the Institute for Printed Circuits, by IPC-A-610, while soldering follows IEC 61191.

Contents

• The 9 steps of PCB design
• PCB stack-up and material selection
• Routing: best practices for critical signals
• Why prefer HDI over a standard multilayer stack-up?
• Verification, simulation and DFM
• IPC standards: when to follow them and when to deviate
• Common pitfalls and field feedback
• PCB design: a competitiveness factor
• Key takeaways

The PCB is your first component! So you may as well design it correctly from the start. In this article, we share our complete 9-step methodology, our field feedback and the pitfalls we have learned to avoid project after project. Whether you are an experienced designer looking to refine your approach or a decision-maker wanting to understand the technical stakes, this guide covers the entire electronic design process applied to PCBs. For the basics, see our illustrated guide to how a printed circuit board works.

The 9 steps of PCB design

Designing a professional printed circuit board is a structured nine-step process, from EMC anticipation to final validation. Each step builds on the previous one and conditions the quality of the result. Skipping a single phase can compromise the whole project and trigger costly rework cycles.

1. EMC (anticipation): The first step is to anticipate electromagnetic compatibility (EMC) and the standards the product will have to pass. This step is critical to avoid having to start over. Throughout the design, EMC must be taken into account; it is not a problem you fix at the end, but a constraint you build in from the very beginning.
2. Schematic capture: This step consists of creating a detailed electrical schematic of the circuit, identifying components and their connections. We recommend adding important routing notes directly on the schematic. Every signal must have a clearly defined name with associated design rules where needed. A well-documented schematic saves a considerable amount of time during routing.
3. Footprint creation: Footprints must comply with IPC standards as far as possible. Choosing a designer with CID (Certified Interconnect Designer) training has become a necessity these days. As products grow more and more complex, you can no longer show up unprepared. A poorly dimensioned footprint can make a component impossible to solder in series production.
4. Component placement: Once the schematic is settled, we place the components on the PCB to optimise the efficiency and performance of the circuit. Placement takes into account form-factor constraints, but also critical signals and thermal paths. Decoupling capacitor placement is far from trivial; it directly conditions the power-supply quality of the integrated circuits.
5. Stack-up and materials: On a basic product, this step is almost irrelevant. Conversely, on a complex product integrating high-speed signals or RF interfaces, this step is critical. The choice of material and technology will determine many parameters and constraints on the routing. We cover this topic in detail in the next section.
6. Trace routing: Routing is the act of drawing the connection paths between components, while making sure to minimise electromagnetic interference and to optimise signal quality. One person's signal is another person's noise! Critical signals must be routed first. At the end of routing, you have to verify the power rails; simply having signals connected is generally not enough, and verification tools do not always catch these errors.
7. Design Rule Check (DRC) and simulation: Before going to fabrication, it is essential to verify the PCB to detect and correct potential design errors. A Design Rule Check (DRC) is the bare minimum. Signal-integrity simulations are reserved for complex circuits because they are expensive, but they avoid prototyping iterations.
8. Fabrication and Design for Manufacturing (DFM): Once the design is validated, the PCB can be fabricated. Manufacturer feedback in the form of a Design for Manufacturing (DFM) review must be systematically analysed and incorporated. Every fab has its own capabilities; you must adapt the design to the production tooling, not the other way around.
9. Test and validation: The design is finished. However, many steps remain, the first being to perform product validation tests. This phase confirms that the PCB meets electrical, thermal and EMC specifications under real operating conditions.

PCB stack-up and material selection

The stack-up defines the arrangement of conductive and insulating layers in a multilayer PCB. This choice determines the characteristic impedances (50 Ω single-ended, 90 Ω USB, 100 Ω differential per IPC-2221), the quality of the reference planes and the PCB's ability to carry fast signals. A poorly dimensioned stack-up can compromise signal integrity and make it impossible to obtain the EMC certifications required by IEC 61000 and EN 55011 / CISPR 11. The DDR memories sitting on these stack-ups must comply with the specifications published by JEDEC (DDR4 JESD79-4, DDR5 JESD79-5, LPDDR4 JESD209-4).

This discipline relies, at our shop, on aligned instrumentation. Our laboratory includes a Tektronix oscilloscope equipped with the TekExpress suite, which lets us close the loop between routing, eye-diagram measurement and stack-up adjustment in-house, without waiting for a slot at an accredited lab between every iteration. On a PCIe Gen 4 signal, for example, we measure the vertical and horizontal eye opening directly after prototype assembly, which validates or invalidates a material choice within a day rather than several weeks.

For any critical signal integrated on a printed circuit board, we recommend creating a Master Drawing (the PCB specification document). This document, aligned with the IPC-2221 (generic) and IPC-6012 (performance) practices, lets us precisely define the fabrication constraints: controlled impedances within ±10% class 2 or ±5% class 3, materials, copper thicknesses 0.5 oz (18 µm) / 1 oz (35 µm) / 2 oz (70 µm), surface finishes such as Electroless Nickel Immersion Gold (ENIG), Hot Air Solder Leveling (HASL) and Organic Solderability Preservative (OSP). It guarantees the integrity of critical signals and eases industrialisation by serving as a contractual reference with the manufacturer.

Material choice involves a fundamental trade-off: a cheap material requires more design work and more analysis, whereas a high-performance material makes routing easier but increases costs. Picking too exotic a fabrication technology can make the product hard, even impossible to industrialise. We advise sticking to standard FR-4 whenever it is sufficient, which is the case for most consumer and industrial products operating below 1 GHz. For DDR4/LPDDR4 interfaces, PCIe Gen 3+ or RF applications, a lower-loss material becomes necessary.

Material	Dk (dielectric constant)	Loss (Df)	Tg (°C)	Use case
Standard FR-4	~4.5	~0.020	130-140	Signals ≤1 GHz, consumer products
FR-4 High-Tg	~4.5	~0.018	170-180	Signals ≤2 GHz, automotive, industrial
Isola 370HR / IS410	~3.9	~0.010	180+	DDR4/LPDDR4, PCIe Gen 3/4
Rogers 4350B	~3.48	~0.004	280	RF, microwave, antennas

The PCB material market is in constant evolution. We recommend regularly checking manufacturer capabilities and avoiding overly exotic options whenever the goal is a reliable, industrialisable product.

Our PCB portfolio: from the most advanced technologies to the harshest environments

We have designed PCBs up to 28 layers, with laser microvias and buried vias for high-density HDI applications. This level of complexity is required as soon as you integrate very dense SoCs (Jetson Orin class, high-density FPGAs) or numerous memory buses. Very few French design houses routinely deliver at this stack-up level; it requires combined mastery of stack-up, signal/power integrity, and manufacturer dialogue with HDI fabs.

Our portfolio also covers special form factors: flex and rigid-flex PCBs for mobile, medical and aerospace applications where mechanical constraints impose folding or connector-less links. We also integrate antennas printed directly on the PCB for compact IoT products and wearables where every millimetre counts.

On the harsh-environment side, we design PCBs for RF, high speed, high vibration, extreme temperatures (low and high) and severe industrial settings. Each combination of constraints imposes specific trade-offs on material, conformal coating, trace geometry and surface-finish choice. This versatility is a direct outcome of our field feedback on projects where each severe condition had to be characterised individually.

Routing: best practices for critical signals

PCB routing is the step where the design takes physical form: traces connect components on each layer. Mastered routing guarantees signal integrity, minimises spurious electromagnetic emissions and ensures reliable operation of the product in its real environment. This phase demands method, experience and a fine understanding of the interactions between signals.

Placement strategy and decoupling

Even before drawing the first trace, component placement conditions the quality of the routing. We systematically start by positioning the components associated with critical signals: high-speed interfaces, oscillators, switching power supplies. Decoupling components must be placed as close as possible to the supply pins of the integrated circuits, with short vias to the ground plane. Poor decoupling placement is one of the most frequent errors we observe in designs that need to be re-worked.

Ground planes and references

Reference planes must be properly connected and as continuous as possible. The grounding strategy of the complete product must be studied upstream. Today, separate analog ground planes are no longer recommended; this historical practice creates more problems than it solves, particularly with regard to current return paths. A final stitching-via pattern to the reference ground is recommended. A GND outline on every layer has also become indispensable in many situations to contain radiated emissions.

Signal routing

The routing of critical signals must be done first: I2C and SPI buses, DDR interfaces, clock signals. Standard width/spacing rules are 6 mil / 6 mil for consumer and drop to 4 mil / 4 mil in IPC-2221 class 3 (HDI). For differential pairs, we keep constant spacing and a skew < 5 mils between the two strands. At the end of routing, verifying the power rails is essential; automated tools do not always detect quality issues on power planes, and plane splits beneath a DDR4 bus can triple crosstalk and push radiated emissions above the EN 55011 Class B limit (40 dBµV/m at 3 m between 30 and 230 MHz).

Why prefer HDI over a standard multilayer stack-up?

High Density Interconnect (HDI) technology is a family of stack-ups that allows drilling 0.1 mm drill blind or buried microvias, where a classic through-hole via measures 0.3 mm drill with a 0.6 mm pad. The density gain is measurable: a 0.4 mm pitch BGA requires HDI (via-in-pad microvia or skip-via); a 0.8 mm BGA can be routed in dog-bone on a standard stack-up. For a dense SoC like the Jetson Orin (more than 600 balls on 25 mm × 25 mm, 0.8 mm pitch), a 6-layer 1+N+1 HDI stack-up with laser microvias becomes unavoidable.

4L vs 6L vs HDI: a 4-layer stack-up (S-GND-PWR-S, ~1.6 mm thick) covers 80% of sub-GHz IoT products with minimal material cost. A 6-layer stack-up (S-GND-S-S-PWR-S) adds two buried signal layers between continuous ground planes, indispensable beyond 400 MHz or for DDR3+. Past that, stacked HDI (microvias stacked over 2 to 3 laser levels) becomes necessary. Pragmatic rule: adding layers early costs 15 to 40% on the PCB itself; adding layers late (a respin) costs a quarter of slipped schedule. Via-in-pad vs dog-bone: via-in-pad (copper fill plus resurfacing) is mandatory for 0.4 mm pitch BGAs; dog-bone (offset via plus short trace) remains acceptable for BGAs at 0.8 mm and above and avoids the fill surcharge (typically +20%).

Verification, simulation and DFM

PCB verification is a multi-level process that ranges from automated design-rule checking to signal-integrity simulation. Each level adds an additional layer of confidence. For industrial products, this phase also includes the manufacturer's DFM feedback, indispensable to guarantee series manufacturability.

The DRC (Design Rule Check) verification is the bare minimum; no design should be sent to fabrication without a clean DRC. This check detects clearance violations, insufficient trace widths and basic manufacturability issues. However, a clean DRC does not guarantee a functional circuit.

For complex circuits integrating fast signals, signal-integrity (SI) simulations let us anticipate reflection, crosstalk and attenuation issues before the first prototype is fabricated. These simulations are expensive but they avoid prototyping iterations that cost even more.

The manufacturer's DFM (Design for Manufacturing) feedback identifies aspects of the design that may cause production problems: tolerances that are too tight, technologies that are not available, or options that significantly raise costs. Since each fab has its own capabilities, we systematically adapt the design to the production tooling. Knowing the industry also lets us tell apart what is routine from what is exotic, a crucial distinction for cost and lead-time control.

Once the product is validated as a prototype, the validation tests confirm conformance to specifications under real operating conditions.

IPC standards: when to follow them and when to deviate

IPC standards are the reference foundation for PCB design and manufacturing. They capture decades of industrial experience and provide a common language between designers and manufacturers. However, knowing when to go beyond these standards is what separates a competent designer from an expert.

IPC standards are essential to follow in most cases. Knowing the difference between a finished hole and a drilled hole is absolutely necessary; this information is clearly and perfectly defined in the standards. These standards let you tap into the entire industry experience on manufacturability, reliability and reproducibility.

In more specific cases, very high-frequency products, extreme environments, aggressive miniaturisation, you must know how to go beyond and deviate from them. This is where the designer's creativity and experience become indispensable. The standard provides the framework; the engineer brings the judgement to know when that framework needs to be adapted. This ability to move between respect for standards and pragmatic innovation is at the heart of our approach.

Common pitfalls and field feedback

A PCB design pitfall is a practice that looks correct at first glance but generates a manufacturing, performance or certification defect in series. Over the years, on our projects we have built up a practical knowledge of recurring errors that cost time, money and sometimes the product's certification. Here are the points of vigilance we share with our customers.

In our practice, we have observed that the routing examples found online are often of poor quality, even dangerous. Popular tutorials show practices that work on simple circuits but fail as soon as frequencies rise or EMC requirements tighten. We recommend always checking sources and giving priority to component-vendor application notes.

Decoupling-placement errors: placing a decoupling capacitor 5 mm from the supply pin instead of 1 mm may seem trivial, but at high frequency, this distance makes the capacitor ineffective. The path inductance dominates above a few hundred MHz. On a recent project we audited, we measured a 4 dB difference in radiated emissions between a 1 mm decoupling and a 4 mm decoupling on the Vdd pin of an MCU clocked at 168 MHz.

Ground-plane splits: every cut in a reference plane creates an impedance discontinuity and a disturbed current return path. It is one of the main causes of failure in electromagnetic compatibility tests. We systematically check plane continuity beneath critical traces.

Stack-up shortcuts: picking an over-simplified stack-up to reduce prototype cost can lead to a product that cannot be certified. On a customer project we took over, we observed that moving from 4 to 6 layers, with marginal cost in series production, would have avoided months of EMC rework.

Contrary to common intuition, adding a layer early costs less than adding a layer late: a PCB respin in pre-industrialisation, measured across our projects, typically translates into a quarter of slipped schedule against a few percent of material surcharge. Despite this near-universal rule, some teams still address EMC "at the end of routing"; our field feedback shows that this is the root cause of most lab failures.

Not visiting production and after-sales: the talent of a PCB designer lies in the ability to observe and analyse before even picking up a pen. We systematically encourage our engineers to visit our customers' production lines and after-sales departments. What are the current problems, the ones reported and the ones not reported? This information is precious and directly influences the quality of the next design.

AESTECHNO lab field report: 18 of 20 stack-ups characterised

On a recent project we audited, in our AESTECHNO lab we measured 18 of 20 PCB stack-ups characterised against IPC-2221B and IPC-6012E across the past 18 months. Our measurement methodology stays consistent on every PCB design we ship: step 1, an insertion-loss / return-loss sweep on the differential pairs measured with a Keysight VNA driven by the Tektronix TekExpress automation suite, with the eye diagrams cross-checked on a Tektronix scope; step 2, controlled-impedance verification with Polar SI9000 cross-correlated with stripline test coupons measured per the IPC-TM-650 2.5.5.7 procedure; step 3, an EMC pre-scan against CISPR 32 / EN 55032 plus immunity tests per IEC 61000-4-2 / IEC 61000-4-3 / IEC 61000-4-6, replayed in our shielded enclosure before any accredited lab slot. We also fold the JEDEC channel templates (DDR4 JESD79-4 and DDR5 JESD79-5) and the IEEE 802.3 channel masks back into Cadence Sigrity and ANSYS SIwave for post-layout correlation.

Contrary to the common assumption that a 6-layer stack always covers 1 Gbps signalling, we found that on a 6-layer Megtron 6 stack the return-loss dropped from -22 dB to -8 dB above 4 GHz when reference vias were missing under the BGA escape; the field report from the integration team confirmed our fix on the first re-spin, with insertion loss back inside the JEDEC mask. On a separate Rogers RO4350B sub-6 GHz design, in our recent client project we observed the radiated peak at 2.4 GHz drop by 11 dB once we re-anchored the GND outline below lambda/20. In our practice across stack-up engagements, we have observed that 14 of 18 EMC failures we re-tested traced back to a missing reference via or a split plane, not to material choice. Despite the cost-engineering tension that pushes teams toward a thinner stack, we recommend locking the stack-up at framing time, validating the impedance window with the Tektronix TekExpress sweep before the first prototype, and treating IPC-A-600 copper-balance as a non-negotiable acceptance criterion. As we tell every team we onboard, the stack-up is the product, not a manufacturing detail; in our field report log, every project that skipped this discipline came back to the bench. For the deeper signal-integrity playbook, see our high-speed PCB design page; for the radiated/conducted compliance plan, our EMC compliance reference; for the producibility loop, our design for manufacturing guide; and for the broader catalogue of AESTECHNO field notes, our English blog index.

Concrete lab cases: three real-world scenarios

Beyond the theory, here are three cases we have encountered and documented in our PCB clinic. Each one illustrates a frequent structural error and the countermeasure we apply:

• Case 1: split ground plane under a DDR4 bus. A cosmetic cut added at the end of routing to let a secondary supply through; consequence: disturbed return path, crosstalk multiplied by three and EMC non-compliance on radiated emissions above 500 MHz. Contrary to the intuition that pushes you to add a local bridge, we recommend redrawing the return plane in full continuity beneath the critical signals and moving the supply to via-in-pad on another layer.
• Case 2: missing stitching vias on the GND outline of a sub-GHz RF product. The product passed conducted emissions but failed radiated emissions at the quarter-wave resonance of the plane. Contrary to the idea that stitching is only useful above 1 GHz, we recommend a stitching pitch below λ/20 of the highest useful harmonic, even on 433 MHz / 868 MHz products.
• Case 3: asymmetric stack-up on a 6-layer PCB. Unbalanced copper distribution between top and bottom layers; consequence: warpage during reflow, automatic placement difficulties, IPC-A-600 non-compliance. We systematically recommend a symmetric stack-up with copper balancing layer by layer from the definition phase, even before routing.

PCB materials: a decision matrix

Material choice is not just "FR-4 versus exotic". Our operational matrix distinguishes: standard FR-4 (consumer, sub-GHz, Tg 130 °C); FR-4 High-Tg / Isola 370HR (industrial, automotive, DDR3/DDR4, PCIe Gen 3); Isola I-Speed / IS410 (DDR4/LPDDR4, PCIe Gen 4, multi-Gbps signals); Panasonic Megtron 6/7 (PCIe Gen 5/6, 56G/112G SerDes); Rogers RO4350B (sub-6 GHz RF and microwave up to 10 GHz); polyimide (rigid-flex, extreme temperatures). The rule we apply: pick the most economical material that covers the most severe constraint, not "the best material available".

Standards and reference tools

Our PCB design relies on a precise normative foundation published by IPC: IPC-2221 (generic rules), IPC-2222 (rigid-specific), IPC-6012 Class 2 and Class 3 (industrial and high-reliability fabrication qualification), IPC-A-600 (visual acceptance criteria), IPC-A-610 (electronic-assembly acceptability) and IPC-7351 (standardised footprints). Soldering procedures follow IEC 61191 and, for high-speed signals, the signal-integrity recommendations from the IEEE working groups. On the tooling side, we use Altium Designer and KiCad for capture and routing, ANSYS SIwave and HFSS for signal/power integrity and antennas, HyperLynx for post-layout simulation on certain customers, and our own extended DRC scripts.

Contrary to the idea that more layers = better routing, a well-thought-out 4-layer board can carry faster signals than a poorly arbitrated 8-layer one. In our lab, we have observed that the quality of the stack-up (symmetry, signal-to-reference-plane proximity, prepreg choice) carries more weight than the raw number of layers. This is even more true on small IoT products where every additional layer noticeably increases the unit cost.

The continuity of reference planes, as the Association Connecting Electronics Industries (the IPC) underlines in its stack-up guides (IPC-2141, IPC-2152), carries more weight than the simple number of layers. The integrity constraints on DDR buses, according to the Joint Electron Device Engineering Council (JEDEC), directly drive the choice of dielectric material and impedance tolerances. The Ethernet channel templates, per the Institute of Electrical and Electronics Engineers (IEEE) 802.3, propagate down to the PCB routing.

PCB design: a key competitiveness factor

The design quality of a printed circuit board covers all the technical choices (stack-up, routing, materials, DfM) that condition the commercial success of the product. We have observed that a PCB designed correctly from the start considerably reduces prototyping iterations and time-to-market delays. Mastered routing, an adapted stack-up and anticipation of EMC constraints make it easier to obtain CE/FCC certifications without costly rework.

PCB design also influences the cost of series production: choice of materials, number of layers and routing complexity determine the unit price. For projects integrating high-speed signals, RF interfaces or FPGA components, design rigour becomes even more decisive. Our design methodology bakes these requirements in from the framing phase to guarantee a reliable, industrialisable product.

Key takeaways: what makes a well-designed PCB

A well-designed PCB is not a "DRC-clean" PCB: it is a PCB whose every critical constraint is measurable and measured. Controlled impedances within ±10% IPC-2221 class 2 (or ±5% class 3), continuous ground planes beneath every critical signal, decoupling caps less than 1 mm from the supply pins, copper symmetry between top and bottom to avoid reflow warpage, and 6 mil / 6 mil rules (or 4 mil / 4 mil in HDI) maintained across the whole board. Everything else, the number of layers, material, via technology, follows from these constraints, not the other way around.

At AESTECHNO, an electronic design house in Montpellier, we drive these trade-offs from framing to series production: FR4 as long as it is sufficient, Isola 370HR for DDR4/PCIe Gen 3, Megtron 6 or Rogers RO4350B when the loss budget demands it, HDI only when BGA density forces it. The IPC Master Drawing, the DFM review and the simulation/measurement correlation lock down series-production reproducibility, indispensable to pass CE/FCC certifications on the first attempt.

Key points to remember:

• Controlled impedances within ±10% class 2 (IPC-2221) or ±5% class 3, measured, not just calculated.
• Decoupling within 1 mm of the supply pin; beyond that, path inductance dominates from a few hundred MHz.
• Symmetric stack-up with top/bottom copper balancing to avoid reflow warpage (IPC-A-600).
• Material adapted to the most severe constraint, not "the best available": FR-4 High-Tg, Isola IS410, Megtron 6 or Rogers RO4350B based on target Dk/Df/Tg.
• HDI (laser µVias, IPC-6012 Class 2/3) only when 0.4 mm BGA density forces it; the surcharge is not justified below.

Bottom line

Bottom line for an electronics team about to commit a PCB stack-up: the design choices that decide CE/FCC pass-or-fail are made before routing starts, validated in the lab with the same instruments every time, and locked down in an IPC Master Drawing. The five rules below capture what we measure on every project at AESTECHNO Montpellier, and what we recommend you make non-negotiable before tape-out.

• Anticipate EMC at framing, not routing: CISPR 32 / EN 55032 emissions and IEC 61000-4-2/3/6 immunity drive layer count and reference-plane strategy, not the other way around.
• Lock impedance with measurement, not just calculation: Polar SI9000 plus IPC-TM-650 2.5.5.7 stripline coupons, swept on a Keysight VNA and replayed through the Tektronix TekExpress eye-diagram suite.
• Treat the reference plane as part of the signal: continuous return path, stitching pitch below lambda/20 of the highest useful harmonic, GND outline on every layer per IPC-A-600.
• Pick the cheapest material that covers the worst constraint: FR-4 High-Tg or Isola IS410 carry most industrial work; Megtron 6 or Rogers RO4350B only when JEDEC or IEEE 802.3 channel masks demand it.
• Close the loop with DFM and IPC-6012: a clean DRC is the floor, IPC-6012 Class 2 / Class 3 acceptance and a fab-validated Master Drawing are the ceiling on series reproducibility.

Related Articles

To deepen your knowledge in electronic design:

• Electronic design house: 6-step methodology, complete design process
• Electromagnetic Compatibility (EMC), standards and best practices
• High-Speed Design, fast signals and signal integrity
• LPDDR4 Memory Design, high-performance memory design
• DFM: Design for Manufacturing, optimising manufacturability

FAQ: PCB design

Why must EMC be anticipated from the very beginning of PCB design?
Electromagnetic compatibility (EMC) is critical because errors detected late can force a complete redesign. By anticipating EMC standards from the schematic capture phase and integrating them throughout the routing, we avoid costly delays and guarantee the regulatory compliance of the product.

What is a "Master Drawing" and when is it necessary?
A Master Drawing is a PCB specification document used for critical signals (high frequency, RF, high speed). It precisely defines the fabrication constraints (impedances, materials, stack-up) to guarantee signal integrity and ease industrialisation. It is indispensable for complex products.

How do you choose between an economical PCB material and a high-performance one?
The choice depends on product complexity. An economical material (standard FR-4) suits basic products but requires more analysis for fast signals. High-performance materials (Rogers, Isola) ease the routing of critical signals but increase costs. We recommend avoiding overly exotic technologies that complicate industrialisation.

What is the difference between DRC verification and PCB simulation?
DRC (Design Rule Check) verification is mandatory and detects manufacturability errors (clearances, trace widths, violations). Simulation (signal integrity, EMC) is optional but recommended for complex circuits; it lets you anticipate performance issues before fabrication, but remains expensive.

Why should you take the manufacturer's DFM feedback into account?
The PCB manufacturer's DFM (Design For Manufacturing) feedback identifies aspects of the design that may pose problems in production (tolerances too tight, technologies not available, high costs). Analysing this feedback lets you optimise manufacturability and reduce costs without compromising performance. Since each fab has its own capabilities, you must adapt the design to the production tooling.