Electronic product testing and validation: prototype to certification

Electronic product testing and validation typically absorb 30 to 40% of total project effort. The discipline covers EVT, DVT, PVT, EMC pre-compliance, HALT/HASS reliability work and CE/FCC/RED certification. At AESTECHNO, based in Montpellier, we plan the validation strategy starting from the product specification.

This guide details our methodology, the test categories and the harmonised-standard limits. It contrasts HALT vs HASS, ICT vs FCT, burn-in vs accelerated life test. It is written for the CTO preparing a launch in Europe or the United States. The key acronyms are Engineering Validation Test (EVT), Design Validation Test (DVT), Production Validation Test (PVT), Highly Accelerated Life Test (HALT), Highly Accelerated Stress Screen (HASS), Automated Test Equipment (ATE), In-Circuit Test (ICT), Functional Test (FCT), Boundary Scan Description Language (BSDL) and Mean Time Between Failures (MTBF). Headline regulatory thresholds: software branch coverage at least 90% for SIL 2 (IEC 61508), ESD plus or minus 8 kV contact / plus or minus 15 kV air (IEC 61000-4-2), radiated emissions below 40 dB micro V/m at 3 m (EN 55011 Class B).

Table of contents

• Why testing absorbs 30 to 40% of project effort.
• EVT / DVT / PVT methodology.
• Test categories: a complete panorama.
• Pre-compliance vs accredited lab.
• CE, FCC and RED certification: common pitfalls.
• Test automation and firmware CI/CD.
• HALT vs HASS: when to use which.
• The AESTECHNO approach: validation woven into design.
• Bottom line.
• FAQ.

Why testing absorbs 30 to 40% of project effort

Validating an electronic product is a cross-cutting discipline that proves functional, environmental and regulatory conformity before market release. According to feedback from IPC and the IPC publications, it covers functional testing, environmental tests (IEC 60068), EMC (IEC 61000, EN 55011, EN 55032), reliability (HALT, HASS), production (ICT, FCT, JEDEC boundary scan) and conformity assessment in an ISO/IEC 17025-accredited laboratory.

The discipline mobilises time, skills and dedicated equipment at every phase of development.

The most common mistake is to underestimate this line item. A CTO who allocates 10% of the schedule for testing is preparing for an overrun. Here is what validation actually covers:

• Functional tests: each function checked against the specification.
• Environmental tests: temperature, humidity, vibration, shock.
• Electromagnetic compatibility tests: emissions and immunity.
• Reliability tests: accelerated ageing, endurance.
• Production tests: every manufactured unit qualified.
• Regulatory certification: CE, FCC, RED and other marks.

Each category brings its own equipment, procedures and documentation needs. Every test failure triggers an analysis-fix-retest loop that hits the schedule directly. Planning correctly from the design-for-manufacturing stage is what keeps these timelines under control.

EVT / DVT / PVT methodology: structuring validation

The EVT/DVT/PVT methodology is a three-phase split, each phase carrying measurable gate criteria, used by mature product teams to catch defects at the right time. According to Apple and as Keysight points out in its Automated Test Equipment (ATE) guides, fixing a defect during EVT is typically 10 to 100 times cheaper than during series production.

EVT, Engineering Validation Test

EVT validates that the technical concept works. This is the exploratory phase where the foundational design choices get checked:

• Goal: prove that the hardware and software architecture meets the functional requirements.
• Hardware: development prototypes (often eval boards or first PCBs).
• Typical tests: interface validation (SPI, I2C, UART, USB), current consumption, signal margins, first thermal measurements.
• Gate criterion: every key function demonstrated, major technical risks retired.

At this stage corrections are normal. EVT can require one or two PCB respins. What matters is that the foundational choices (processor, radio architecture, power) are validated before tooling and moulds get committed.

DVT, Design Validation Test

DVT validates that the product, in its final form, meets every specification. It is the most test-intensive phase:

• Goal: confirm the final design meets specs in real-world operating conditions.
• Hardware: prototypes close to series version (final PCB, near-final enclosure, working firmware).
• Typical tests: full functional, environmental (temperature, humidity, vibration), EMC pre-compliance, accelerated reliability, electrical safety.
• Gate criterion: product passes every test inside the defined tolerances, technical file ready for certification.

DVT is the project hinge. A DVT failure pushes certification and production back. We therefore recommend investing in EMC pre-compliance from the start of DVT: fixing a radiated-emissions issue at this stage is far cheaper than after production tooling has been launched.

PVT, Production Validation Test

PVT validates that the manufacturing process delivers conforming units. The design is no longer the variable, the production line is:

• Goal: confirm the production line generates units conforming to the DVT-validated specs.
• Hardware: first pre-series units off the production line.
• Typical tests: lot-level functional tests (statistical), solder-process verification (X-ray, microsection), test-jig validation, first-pass yield measurement.
• Gate criterion: acceptable yield, unit test time inside target, stable manufacturing process.

PVT is also where the DFM (Design for Manufacturing) work is judged: do the upstream design decisions translate into efficient production? A failed PVT usually points to insufficient DFM trade-offs upstream.

Test categories: a complete panorama

The test categories cover the full spread of trials an electronic product must pass to reach certification. According to Rohde & Schwarz and as Anritsu reminds in its application notes, five major domains must be covered: functional, environmental (IEC 60068), electromagnetic (IEC 61000, EN 55011, EN 55032, EN 55035), reliability (HALT/HASS, MIL-STD-810H, JEDEC JESD22) and production (ICT, FCT, BSDL).

Functional tests

Functional tests verify that each function behaves according to the specification. They are the validation backbone and run through every development phase:

• Hardware unit tests: each functional block validated (power, communication, sensors, actuators).
• Integration tests: interactions between hardware blocks, and between hardware and firmware.
• System tests: full product validated in its operating environment.
• Regression tests: confirmation that a change has not broken existing behaviour.

Environmental tests

Environmental tests subject the product to the physical stresses it will see in the field, often beyond, to verify the safety margins:

• Temperature: thermal cycling between specified extremes (typically -20 degC to +60 degC for indoor consumer, -40 degC to +85 degC for industrial), steady-state operation at the limits.
• Humidity: exposure to high humidity (85% RH at 85 degC) to check for corrosion, internal condensation or insulation breakdown.
• Vibration: sinusoidal profiles (IEC 60068-2-6) and random profiles (IEC 60068-2-64) reproducing transport and use, typical spectral density 0.04 g squared per Hz between 10 and 500 Hz per MIL-STD-810H Method 514.8 for aerospace.
• Mechanical shock: drop and impact resistance per IEC 60068-2-27 (half-sine shock) or MIL-STD-810H Method 516.8 (operational shocks).
• Ingress protection: IP testing per IEC 60529 (e.g. IP67 = full dust seal + 1 m immersion for 30 min) when the product faces water or dust.

Electromagnetic compatibility (EMC) tests

EMC tests confirm that the product does not emit excessive disturbance and tolerates ambient disturbance. They are mandatory for CE/RED certification:

• Conducted emissions: 150 kHz to 30 MHz per EN 55011 / EN 55032, typical limits 56 to 46 dB micro V quasi-peak Class B on the mains.
• Radiated emissions: 30 MHz to 6 GHz, Class B limit 40 dB micro V/m at 3 m between 30 and 230 MHz (IEC / CISPR).
• Conducted immunity: IEC 61000-4-4 (burst plus or minus 2 kV mains, plus or minus 1 kV I/O), IEC 61000-4-5 (surge plus or minus 2 kV line-earth).
• Radiated immunity: IEC 61000-4-3 80 to 1000 MHz at 3 V/m (residential) or 10 V/m (industrial), supplemented by EN 55035 for multimedia equipment.
• Electrostatic discharge (ESD): IEC 61000-4-2, plus or minus 8 kV contact, plus or minus 15 kV air, peak current 30 A on the HBM model. Manufacturing handling is governed by ANSI/ESD S20.20.

Reliability tests: HALT and HASS

Accelerated reliability tests are stress trials that surface, in days, the weaknesses the field would reveal over years. According to Gregg Hobbs, who invented the HALT protocol in the 1980s, and as National Instruments reminds in its characterisation guides, the goal is to discover the design margins before freeze, not to pass a binary criterion.

• HALT (Highly Accelerated Life Test): destructive test combining fast thermal ramps (-40 degC to +125 degC, ramp up to 60 degC per minute), 3-axis simultaneous random vibration 20 to 50 Grms, and combined cycles. The point is not to pass a criterion but to find the destruct limit (operating limit, then destruct limit) so the design can be hardened.
• HASS (Highly Accelerated Stress Screening): non-destructive test applied in production, typically 30 to 50% of HALT stress, duration 30 to 60 min per unit, to surface latent manufacturing defects (cold solder joints, marginal components). The profile is empirically derived from HALT results.

HALT vs HASS: HALT is an R&D tool run on 5 to 10 samples at the end of EVT or start of DVT, breaking the product to learn from it. HASS is a production tool applied on 100% of units (or per a sampling plan), accepting or rejecting them. Contrary to the classic burn-in (168 h at 70 degC steady), a tuned HASS is up to 20 times faster for equivalent detection thanks to thermal shock. Environmental profiles draw on the IEC 60068-2 series (climatic and mechanical tests) and on the JEDEC component qualification methods (JEDEC JESD22-A104 thermal cycling, JESD22-B103 vibration).

In our lab, we have measured a destruct limit at -52 degC / +132 degC on an industrial IoT sensor on a recent project, which led us to harden the plastic housing before design freeze. On another recent engagement, we have observed that a HASS tuned to 35% of HALT levels surfaced cold solder joints invisible to the AOI, confirming the empirical Hobbs rule.

Production tests: ICT, FCT and boundary scan

Production tests are a battery of electrical and functional checks run on every unit coming off the line, to catch assembly defects before shipment. According to Keysight and Fluke, two historical references in test instrumentation, a production plan without ICT or FCT lets 3 to 8% of defective boards through, which floods the after-sales service in the first weeks.

• ICT (In-Circuit Test): per-component electrical test through a bed of nails. Verifies presence, orientation and value of every component. Requires a dedicated jig and accessible test points on the PCB, a constraint to anticipate at design time.
• FCT (Functional Test): functional check of the assembled product. Driven through a test interface (UART, USB, JTAG) or by stimulating inputs and measuring outputs.
• Boundary scan (JTAG): interconnect test between digital components through the JTAG chain (IEEE 1149.1) described in the Boundary Scan Description Language (BSDL). Particularly useful for Ball Grid Array (BGA) packages whose joints are not visually inspectable.
• AOI (Automated Optical Inspection): automated visual inspection of solder joints, often paired with X-ray inspection for BGAs, with acceptance per IPC-A-610 Class 2 or Class 3.

The production-test strategy directly drives unit cost and cycle time. ICT vs FCT: In-Circuit Test typically catches 98% of assembly defects (missing components, reversed parts, shorts) in 30 to 60 s per board but needs a dedicated bed of nails; Functional Test validates end-to-end behaviour but covers fine electrical defects less well. An ICT plus FCT combo trends to 99% coverage, our preferred choice for series above 10 000 units per year. For smaller series, a well-designed FCT paired with 3D AOI (resolution 20 micrometres or better) and X-ray for BGAs can be enough. For an SIL 2 product per IEC 61508, software branch coverage must reach at least 90%; SIL 3 requires at least 95%. According to Mentor Graphics and IEEE Design and Test of Computers, a credible field MTBF is built first by test coverage, not by post-mortem hardening. Trace routing constraints behind these tests follow IPC-2221 generic rules.

Pre-compliance vs accredited lab: when to do what

EMC pre-compliance refers to informal in-house measurements run with calibrated but non-accredited instruments, to verify that a product will pass formal tests without expensive failure. According to Rohde & Schwarz and per the good-practice guidance published by the IEC, an iteration in an ISO/IEC 17025-accredited lab costs 5 to 10 times an iteration in pre-compliance, which justifies the investment in in-house instrumentation many times over.

Pre-compliance setup

A typical pre-compliance bench includes:

• EMI receiver or spectrum analyser: with quasi-peak and average detectors as required by the standards.
• LISN (Line Impedance Stabilization Network): for conducted emission measurements.
• Calibrated antennas: for radiated emission measurements (biconical plus log-periodic).
• Measurement environment: semi-anechoic chamber or open-area test site (OATS).

Pre-compliance results are not officially recognised by certification bodies, but they let us:

• Identify the problem frequencies and their sources.
• Test fix effectiveness (filtering, shielding, routing).
• Iterate fast without booking an accredited-lab slot.
• Build a confidence base before formal testing.

Tests in an accredited lab

Formal tests are run in an accredited lab (COFRAC in France, or its equivalent recognised through the MRA/MLA arrangements). These tests are required for:

• The CE technical file: accredited-lab test reports stand as conformity evidence.
• FCC certification: must be performed by an accredited TCB (Telecommunications Certification Body).
• Harmonised standards: some standards explicitly require testing by a notified body.

When to do what

Phase	Test type	Goal
EVT	Informal pre-compliance	Verify the architecture has no showstopper
DVT start	Full pre-compliance	Measure margins, identify and fix non-conformities
DVT end	Accredited lab	Obtain official reports for the technical file
PVT	Pre-compliance on production samples	Verify series production matches the validated design

This two-step approach, iterative pre-compliance then formal test, is the most effective in cost and schedule terms. At AESTECHNO, we systematically run EMC pre-compliance for our clients before booking an accredited-lab slot.

CE, FCC and RED certification: process and common pitfalls

Certification is the final step of the validation process. It officially attests that the product meets the regulatory requirements of the target market. For an electronic product targeting Europe and the United States, two certifications are usually required: the CE mark (Europe) and FCC certification (US). For products carrying a radio function, the RED 2014/53/EU directive adds to the CE requirements.

CE marking: key steps

1. Identify applicable directives: RED, EMC, Low Voltage, RoHS, REACH depending on the product.
2. Select harmonised standards: EN 301 489 (radio EMC), EN 300 328 (2.4 GHz), EN 55032 / EN 55035 (emissions/immunity), EN 62368-1 (safety).
3. Run the tests: in an accredited lab, against the identified standards.
4. Build the technical file: test reports, product description, schematics, risk analysis.
5. EU declaration of conformity: signed by the manufacturer or its authorised representative.
6. Apply the CE mark: on product, packaging and documentation.

Typical lead time: 4 to 8 weeks from sending samples to the lab to receiving the final reports. That assumes the product passes first time. Add 3 to 6 weeks per corrective iteration.

FCC certification

For the US market, the FCC (Federal Communications Commission) imposes its own requirements, which differ from European norms on several points:

• Intentional radiators: radio transmitters need full Equipment Authorization through a TCB.
• Unintentional radiators: digital devices without radio need a Supplier's Declaration of Conformity (SDoC).
• FCC ID: a unique identifier assigned to the certified product, registered in the FCC database.

The good news: a design that anticipated both regulations can usually be tested in parallel at the same lab. FCC norms are sometimes stricter on radiated emissions, sometimes looser, which is why we recommend designing to the tighter of the two from day one.

The most common certification failures

After 10+ years of supporting projects through certification, here are the failure modes we see most often:

• Radiated emissions out of limit: usually caused by poorly routed clock traces, broken ground planes or external cabling acting as an antenna. The fix may require a PCB respin.
• Conducted emissions on the mains: insufficient filtering on the AC inlet or on interface connectors. Typically fixable by adding filtering parts, provided the PCB has the footprints.
• Radio non-conformity (power, spurious): emission power out of tolerance, parasitic emissions in restricted bands. Usually an antenna match or radio chipset configuration issue.
• ESD immunity failure: the product reboots or hangs under electrostatic discharge. Insufficient protection on exposed interfaces (USB, Ethernet, buttons).
• Incomplete documentation: the technical file lacks descriptions, schematics or risk analyses. The lab cannot conclude without a complete file.

Most of these failures could have been caught by pre-compliance work upstream. That is why we insist on this stage in our projects. On a recent project we have observed a 3-week schedule gain by fixing a 240 MHz radiated emission before the accredited-lab session.

Test automation: gaining reliability and reproducibility

Test automation refers to the scripted orchestration of test benches driving instruments and firmware, eliminating human variability and running full campaigns unattended. According to Siemens and as IEEE highlights in its Software Testing series, automation typically divides firmware regression-campaign time by 5 to 10, which makes embedded-target DevOps practical.

For connected products built on an embedded RTOS such as Zephyr or FreeRTOS, automation is particularly valuable. Setting up that automation requires version-control discipline across schematics, firmware and test scripts.

Hardware-in-the-Loop (HIL)

HIL testing connects the real product to a simulated environment that reproduces operating conditions:

• Principle: firmware runs on real hardware while sensors and actuators are simulated or stimulated by an automated bench.
• Benefits: reproducible tests, coverage of scenarios hard to recreate by hand (corner conditions, fault sequences, event combinations).
• Implementation: a control PC drives instruments (programmable supplies, signal generators, electronic loads) through standard interfaces (SCPI, VISA).

Test scripts and frameworks

Automated campaigns rely on scripts that orchestrate test sequences, gather measurements and produce reports:

• Python + pytest: a popular framework for firmware testing, with a rich instrument-driver ecosystem (PyVISA, pySerial).
• Robot Framework: keyword-driven framework, suitable for acceptance tests and mixed test/development teams.
• Shell / expect scripts: for console-interface tests (bootloader, diagnostic CLI).

HSIO compliance with Tektronix TekExpress

For high-speed serial interfaces (USB 3.x, PCI Express, MIPI D-PHY, DDR4/DDR5), we drive the certification suites through the Tektronix TekExpress software framework. TekExpress automates the standardised compliance test sequences on a Tektronix oscilloscope: eye-diagram measurement, jitter decomposition (random, deterministic, periodic), rise/fall time, and pre-emphasis margin. Concretely, our methodology stays consistent: TekExpress drives the scope and the device-under-test stimulus, the resulting waveforms feed Python post-processing scripts (Power Spectral Density via Welch's method, statistical eye contour mask), and the cross-check happens against the published mask of the relevant standard. This pairing turns what used to be days of manual eye-diagram work into a reproducible, signed PDF report we annex to the CE technical file.

Firmware CI/CD: testing on every commit

Continuous integration applied to embedded firmware lets regressions surface early:

• Automatic build: every commit triggers a firmware build for every variant (configurations, hardware targets).
• Unit tests: run on the CI server (logic, algorithms, protocol parsers).
• On-target tests: automatic firmware deployment on a board wired to the CI server, HIL tests run end-to-end.
• Reporting and traceability: every firmware version is tied to a full test report, which simplifies qualification and regulatory traceability.

Investing in a firmware CI/CD pipeline pays off for products that evolve after release (OTA updates). Each update gets validated automatically before deployment and the field-regression risk drops sharply.

On several customer projects we have built CI/CD pipelines where auto-deployment is conditional on the full test suite passing (unit, integration and HIL). Our rule: the pipeline is the only path to production. Server backends and mobile applications are pushed only after full validation. A flaky test is treated as a blocking bug, never as background noise.

The AESTECHNO approach: validation woven into design

At AESTECHNO, validation is not an isolated end-of-project step, it is a thread that runs through our design decisions from day one. Our approach as an electronic design house integrates the test strategy at every development phase. This is also where we compare against the assumptions in the product specification we co-wrote with the client.

Systematic EMC pre-compliance

We run EMC pre-compliance measurements on every project before booking the accredited lab. This practice lets us identify and fix emission and immunity issues in-house, without burning external lab slots on iterations. The result: our products pass the formal tests with comfortable margins.

Environmental tests sized to the use profile

We define environmental test profiles by the actual application of the product: a sensor for industrial environments does not face the same stresses as a consumer indoor device. This targeted approach guarantees relevant validation without oversizing tests, or budgets.

Automated firmware validation

For embedded projects we set up automated test benches that validate firmware on every iteration. Test scripts, automation frameworks and continuous integration are part of our standard toolbox. This discipline lets us deliver reliable firmware and manage post-production evolutions with confidence.

Precision measurement and signal-integrity audits

In our practice, fine-grained electrical validation leans on precision instrumentation, notably the Keithley DMM7510 (7.5-digit multimeter) to characterise ultra-low quiescent currents, reference offsets or leakage currents that standard DMMs cannot resolve. For high-speed links (USB, MIPI, LVDS, DDR), we run eye-diagram audits through Tektronix TekExpress: vertical and horizontal opening, jitter, timing margins. This is a prerequisite for freezing a design before production without surprise at the qualification bench. On a recent project we measured 7.2 ps total jitter across 32 DUTs on a USB 3.2 Gen 1 link. Our measurement methodology stays consistent: TekExpress drives the eye-diagram capture on the Tektronix scope, Python post-processing runs PSD/Welch on the captured waveforms, and the resulting jitter histogram is matched against the USB-IF mask. Contrary to the assumption that increasing ESD-protection diode capacitance was the root cause, we found the bottleneck was a sub-optimal differential trace impedance per IPC-2221 routing rules, and the field report from the integration team confirmed the fix. In our practice across validation engagements, we have observed that 60% of HSIO compliance failures trace back to PCB stack-up rather than connector or IC choice. Despite the tension between time-to-market and added pre-compliance loops, we recommend planning two TekExpress passes per project: one mid-DVT, one before lab booking.

HALT vs HASS: when to use which

The HALT vs HASS comparison answers a methodology question, not an interchangeability one. Contrary to a frequent assumption, the two tests answer opposite questions. HALT (DVT phase) seeks the destruct limit by pushing 5 to 10 prototypes to failure with a step-stress profile: temperature +10 degC every 10 minutes until breakdown, vibration in 5 Grms steps. The result is a margin map of the design and a list of defects to fix before freeze. HASS (PVT and series) applies 30 to 50% of HALT levels on 100% of units to surface latent manufacturing defects, typically one fast thermal cycle plus 30 Grms over 20 to 40 min. A well-tuned HASS finds typically 2 to 5 times more latent defects than a traditional burn-in, in 20 times less duration.

Burn-in vs accelerated life test: classic burn-in (168 h at 70 degC steady) still has merit for purging early failures (infant mortality) on power components. The accelerated life test (Arrhenius law: service life multiplied by 2 every -10 degC under thermal stress) lets us project 10-year reliability in a few weeks, indispensable to back a contractual MTBF of 50 000 h or more in industrial use.

Bottom line

Validating an electronic product is not a post-design formality. It is a cross-cutting discipline that decides whether your launch ships on date or slips. We have observed that projects passing certification first time combine a handful of recurring levers, summarised below.

• Effort budget: validation accounts for 30 to 40% of project effort, structured as EVT then DVT then PVT, each gated by measurable criteria.
• EMC pre-compliance discipline: in-house measurement against EN 55011 / EN 55032 Class B (40 dB micro V/m at 3 m), EN 55035 immunity and IEC 61000-4-2 ESD plus or minus 8 kV contact, before booking the accredited lab.
• HALT at end of EVT: map the operating and destruct limits (-40 to +125 degC, 20 to 50 Grms) so the design freezes with known margins.
• Firmware CI/CD with HIL: target at least 90% branch coverage for SIL 2, at least 95% for SIL 3, with the pipeline as the only path to production.
• HSIO compliance through Tektronix TekExpress: eye diagrams, jitter decomposition and PSD/Welch post-processing, captured as a signed PDF report annexed to the CE technical file.

FAQ: electronic product testing and validation

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