USB 3.2 vs USB4 in 2026: 20-40 Gbps, Type-C, design choice

A product labelled "USB 3.2" may deliver 5 Gbit/s or 20 Gbit/s, and we routinely meet customers convinced they have specified Gen 2 when the chosen controller only supports Gen 1. USB 3, also called SuperSpeed USB, links peripherals, sensors and embedded systems at speeds from 5 to 20 Gbit/s; between versions renamed by the USB-IF, connector variants and PCB-routing constraints, integrating a reliable USB 3 link remains a real design challenge. This guide walks through every version, the signal-integrity constraints and the practices we use at AESTECHNO to build reliable links from the very first prototype.

What is USB 3 (SuperSpeed)?

USB 3, or SuperSpeed USB, is the third major generation of the Universal Serial Bus standard published by the USB Implementers Forum (USB-IF). It reaches a raw bit rate of at least 5 Gbit/s, ten times more than USB 2.0 (480 Mbit/s). Specified by the USB Implementers Forum (USB-IF), the architecture moves to full-duplex operation with two dedicated differential pairs (TX+/TX-, RX+/RX-), a clear technical break from the half-duplex USB 2.0 released in April 2000.

Contrary to a widespread misconception, USB 3 does not abandon previous generations: it is fully backward-compatible with USB 2.0 and USB 1.x. A USB 3.x device plugged into a USB 2.0 port works normally, but at USB 2.0 speed (480 Mbit/s). That backward compatibility relies on keeping the original D+/D- contacts inside the connector, alongside the additional SuperSpeed pairs (TX+/TX-, RX+/RX-). In practice, this means a single physical connector carries two logically independent buses, an important point for PCB design.

USB 3.x versions and generations: untangling the names

USB 3 nomenclature is the official grid that describes each generation (Gen 1, Gen 2, Gen 2×2) and its raw bit rate. It calls for careful reading because the USB-IF has renamed USB 3 versions several times, sowing confusion among designers and buyers alike. Defined by the USB Implementers Forum (USB 3.2 specification rev 1.1, June 2022), the official nomenclature unifies the older USB 3.0 and USB 3.1 names under the USB 3.2 banner, with three speed grades (Gen 1, Gen 2, Gen 2×2). Understanding this mapping is essential when writing a precise specification and avoiding supplier-side ambiguities.

The table below maps each current official name to its former name, raw bit rate, line coding, effective throughput and number of lanes, so that Gen 1 (5 Gbit/s), Gen 2 (10 Gbit/s) and Gen 2×2 (20 Gbit/s) can be told apart at a glance in any datasheet or supplier quote.

The key takeaway: a product simply labelled "USB 3.2" with no generation tag may deliver anywhere between 5 Gbit/s and 20 Gbit/s. We always recommend specifying the exact generation (Gen 1, Gen 2 or Gen 2×2) in technical documents and product datasheets. That discipline prevents supplier disputes and on-bench performance surprises. Line coding plays a major role too: moving from 8b/10b (80% efficient) to 128b/132b (97% efficient) is why the effective throughput of Gen 2 is well above a simple theoretical doubling of Gen 1.

USB connectors: picking the right form factor

The USB connector choice is a trade-off between target protocol, mechanical footprint, robustness over insertion cycles and compatibility with the cable ecosystem on the market. We validate this choice as early as the specification phase because it drives PCB routing, enclosure mechanics and the user experience. Pin by pin, see our USB-C pinout, all 24 pins and our USB Type-A, Type-B, Mini and Micro pinout.

At AESTECHNO, we help our customers select the best-suited connector by factoring in footprint, mechanical constraints (insertion/extraction cycles) and the available cable ecosystem.

Three connector families cover SuperSpeed designs today: USB Type-C, reversible and the unavoidable standard for new products; USB Type-A, still common in industrial equipment and robust in harsh environments; and USB Micro-B SuperSpeed, increasingly rare and displaced by Type-C. The table further down compares them on maximum protocol, robustness and Power Delivery.

• USB Type-C: reversible, compact, supporting up to USB 3.2 Gen 2×2 (20 Gbps) and USB4 (40 Gbps). It is the unavoidable standard for new products. A caveat: a Type-C connector does not automatically mean USB 3 throughput - the protocol version depends on the controller and the cable.
• USB Type-A: still very common in industrial equipment and consumer peripherals. Supports up to USB 3.2 Gen 2 (10 Gbps). Its mechanical robustness makes it a sound choice for harsh environments.
• USB Micro-B SuperSpeed: mostly used on external hard drives and a handful of embedded devices. Increasingly rare in new designs, displaced by Type-C.

PCB design for USB 3: challenges and best practices

USB 3 PCB design is the discipline that secures SuperSpeed signal integrity at 5, 10 or 20 Gbit/s. It demands strict impedance control, a properly engineered stackup, disciplined differential routing and proactive Tektronix TekExpress compliance checks well beyond simply picking a connector. In our practice at AESTECHNO, we treat the stackup, the routing rules and the channel budget as one coupled problem, validated against USB-IF SI templates before any board is sent to fabrication.

The four subsections below follow that order: differential pair impedance control at 90 Ω ±10%, routing constraints such as intra-pair length matching and via minimisation, ESD protection that does not close the eye, and signal integrity at 5 Gbit/s and beyond.

Differential pair impedance control

Defined by the USB Implementers Forum (section 6.7 of the USB 3.2 specification), the SuperSpeed differential pairs (TX+/TX- and RX+/RX-) must hold a differential impedance of 90 Ω ±10%. That parameter depends on trace width, intra-pair spacing, dielectric thickness and dielectric constant (Dk). We always work with the PCB fabricator to validate the stackup and obtain a controlled-impedance report (TDR measurement) before release to production. Even a few-ohm impedance mismatch causes signal reflections that degrade the bit-error rate (BER target < 10^-12 for a SuperSpeed link) and can render the link unstable.

Routing constraints

USB 3 routing imposes several strict rules we apply on every project:

• Intra-pair length matching: the two traces of a single differential pair must match in length within ±5 mils (±127 µm) to avoid timing skew.
• Via minimisation: every layer transition (via) introduces an impedance discontinuity. In line with IPC-2221B and IPC-6012 rules for high-frequency PCBs, we use low-inductance vias (back-drilled or micro-vias) when the design calls for it.
• Continuous reference plane: the differential pairs must travel above an uninterrupted ground plane. Any cut in the return plane degrades signal integrity and increases electromagnetic emissions.
• USB 2.0 / USB 3.0 separation: the D+/D- signals (USB 2.0) must be routed apart from the SuperSpeed pairs, with sufficient spacing to prevent crosstalk.
• Maximum PCB length: we recommend keeping USB 3.x traces under 15 cm to limit attenuation, especially on inner layers with standard FR-4 dielectric.

These constraints mirror those we encounter on other high-speed buses such as PCI Express (whose specification is governed by PCI-SIG), which lets us share routing know-how within a single project. The signal-integrity measurements we run lean on the methodology published by IEEE (802.3 and 370 for interconnect characterisation).

ESD protection and immunity

USB ports are exposed directly to the outside world. Electrostatic-discharge (ESD) protection is therefore mandatory, both for product robustness and for compliance with CE marking (the FCC has no ESD immunity test). Specified by the International Electrotechnical Commission (IEC 61000-4-2), robustness requires that an accessible port survive a discharge of ±8 kV in contact mode and ±15 kV in air (level 4). We systematically place ESD-protection components (TVS diodes) as close as possible to the connector, and we make sure their parasitic capacitance stays low enough (typically < 0.5 pF per line, as recommended by STMicroelectronics on their low-capacitance ESDALC6V1 TVS) so they do not degrade signal integrity at 5 or 10 Gbps. Selecting these components is part of our overall electromagnetic compatibility approach.

Signal integrity at 5 Gbps and beyond

At 5 Gbps (USB 3.2 Gen 1), signal rise time is on the order of a hundred picoseconds. At that speed, every discontinuity along the signal path - a 90 degree bend, a poorly optimised via, a layer change without a return via - can trigger reflections and crosstalk. For Gen 2 (10 Gbps) and Gen 2×2 (20 Gbps) generations, those effects become even more critical. We always recommend a signal-integrity (SI) simulation upstream of the routing to validate stackup choices and routing paths. This approach, also covered in our high-speed design notes, lets us anticipate problems before the first prototype is fabricated.

USB 3 vs other high-speed interfaces

USB 3 is not the only high-speed interface available to electronics-product designers. Depending on topology, communication distance and throughput requirements, other buses may be a better fit. The comparison below positions USB 3 against the alternatives commonly seen in embedded and industrial systems.

USB 3.2 Gen 2, PCI Express 4.0, Thunderbolt 4 and 10GbE Ethernet each win on a different axis. USB 3.2 Gen 2 reaches 10 Gbit/s over a 3 m passive cable with hot-plug support, PCI Express 4.0 offers 16 GT/s per lane but stays on the board at around 30 cm, Thunderbolt 4 reaches 40 Gbit/s in a daisy-chain topology, and 10GbE covers 100 m over Cat6a copper. The table details these criteria side by side.

For board-internal links (SoC to memory, FPGA to controller), PCI Express often remains the best pick thanks to its per-lane bandwidth and low latency. As soon as an external connector and hot-plug operation come into play, USB 3 offers an excellent throughput-to-cost ratio backed by a mature cable and peripheral ecosystem. On the host side, USB 3 controllers integrate equally well into MCUs such as the STM32H7, into NVIDIA Jetson Orin SoCs or onto Intel x86 platforms, driven by a USB stack on Linux, FreeRTOS or Zephyr depending on the performance budget.

Common pitfalls and field feedback

Integrating a USB 3 interface into a professional product is full of traps that only field experience prepares you for. At AESTECHNO, we have observed that most USB 3 certification failures trace back to the PCB routing or to mismatched component choices, well before the enclosure stage.

Our portfolio covers every USB version still relevant: USB 2.0, USB 3.0, USB 3.1 and USB 3.2, with a fine-grained understanding of fallback and negotiation pitfalls. We have, for example, designed a custom industrial computer based on Intel Core i5 combining several USB 3.x ports, a heavily loaded PCIe bus (up to Gen 5 on our most recent designs) and internal SATA links - an architecture where every high-speed domain interacts with the others through the power backplane and the ground planes.

Simulation and measurement before USB-IF testing

We simulate high-speed buses, USB 3.x included, in ANSYS before final routing in Altium Designer, which lets us catch insufficient margins caused by a sub-optimal stackup or an over-capacitive TVS. What most people miss is that an over-capacitive TVS destroys the eye long before the trace length does. In our practice, we apply TDR (Time Domain Reflectometry) measurements per IPC-TM-650 on every USB 3 prototype before submitting it for USB-IF testing. Our deliverables comply with IPC-2221, IPC-6012 (rigid PCB qualification) and IPC-A-610 (assembly acceptance criteria).

• Naming confusion: in our practice, we routinely meet customers convinced they have specified a USB 3.2 Gen 2 (10 Gbps) interface when the chosen controller only supports Gen 1 (5 Gbps). Always check the controller datasheet, not the marketing label on the connector.
• Uncertified cables: a USB-C cable bought online may very well only support USB 2.0. We recommend systematically validating with USB-IF certified cables and documenting part numbers in the specification.
• Attenuation on long traces: beyond 10 to 15 cm on standard FR-4, SuperSpeed signal attenuation becomes significant. On a design with an integrated USB hub, the cumulative trace length between controller, hub and connector easily exceeds that limit. We then move to a low-loss dielectric (Megtron, IS410) or insert re-drivers.
• ESD overlooked: a USB port without TVS protection rarely passes the IEC 61000-4-2 electrostatic-discharge tests required for CE marking. Beware: a TVS with too much parasitic capacitance degrades the signal at 5 Gbps.
• Backward compatibility under-tested: a USB 3 product must operate correctly in USB 2.0 mode (fallback). We always include validation tests covering both modes.
• Thermal issues on USB hubs: USB 3 hub controllers with several downstream ports can dissipate significant power. In our practice, we always add copper dissipation planes and verify temperature under maximum-load conditions.

USB-C Power Delivery and USB4: where is it heading?

USB-C Power Delivery is the power-negotiation protocol that allows up to 240 W on a single Type-C cable, while USB4 is the tunneling-based generation at 40 or 80 Gbit/s that unifies data, video and power on the same physical port. Together, they define the modern USB-C ecosystem, where a single connector carries DisplayPort, PCIe and USB streams negotiated dynamically between host and device. This convergence is reshaping how industrial and consumer products specify their I/O.

USB Power Delivery (USB PD) dynamically negotiates voltage and current between two devices over the CC channel of the Type-C connector. Published by the USB Implementers Forum (USB PD 3.1 specification), the latest revision introduces Extended Power Range (EPR), pushing available power up to 240 W (48 V / 5 A). For industrial products, that capability opens up new power-architecture options.

USB4: tunneling at 40 and 80 Gbit/s

USB4 is built on the Thunderbolt 3 protocol (transferred from Intel to the USB-IF) and reaches 40 Gbit/s on two differential pairs through a tunneling mechanism. Defined by the USB Implementers Forum (USB4 v2.0 specification), it natively supports alternate modes (Alt Mode) for transporting DisplayPort streams, allowing 4K/8K monitors to connect over a single USB-C cable. USB4 v2.0 raises the ceiling to 80 Gbit/s (and 120 Gbit/s asymmetric), positioning USB as a universal interface for data, video and power.

The USB software stack on the embedded firmware side must be adapted to support these advanced features, in particular PD negotiation and alternate modes.

USB 3 in your products: a strategic decision

The USB interface of a product is a strategic lever that directly affects competitiveness and user experience. The right call comes from aligning version, connector and performance with the targeted market positioning, while keeping a close eye on the ESD, EMC and signal-integrity envelope each generation demands. In our practice, we frame this as a four-axis trade-off: throughput, mechanical robustness, certification cost and ecosystem maturity, scored against the product roadmap before any controller is locked in.

This is not purely a technical choice. A USB 3.2 Gen 2 throughput (10 Gbps) enables 4K video transfer, fast external-storage connections or real-time aggregation of sensor data - features that differentiate a product on the market.

User expectations and compliance validation

Beyond raw performance, users now expect a fast and versatile USB-C connection. A product limited to USB 2.0 while competitors offer SuperSpeed risks looking dated. In our design process, we analyse these dimensions from the scoping phase, in step with the product specification, to give you a relevant and durable product positioning. A rigorous test and validation strategy then ensures the finished product complies with USB-IF specifications. For the underlying high-speed PCB and EMC ground rules, our high-speed PCB design notes go deeper, and our USB-C Power Delivery for industrial products piece covers the PD 3.2 negotiation specifics. For broader bus context, see our PCI Express bus reference and the full AESTECHNO blog.

Bottom line

The Bottom line section is the executive summary of every operational lesson distilled in this guide, condensed into five takeaways an engineering manager can act on this week. Each bullet maps to a measurement, a component family or a USB-IF document we cite earlier in the article.

• Spec the generation, not the marketing label. Always write "USB 3.2 Gen 2 (10 Gbit/s)" or "USB4 Gen 3x2" in the datasheet and BOM, never just "USB 3.2" or "USB-C", to prevent supplier ambiguity.
• Budget the channel before the board. Build the insertion-loss / return-loss budget from connector to controller, validate against USB-IF SI templates, and pre-allocate space for a Texas Instruments, Diodes Inc or Cypress / Infineon redriver from 12 cm onward.
• Run TekExpress continuously. Treat the Tektronix TekExpress USB-IF compliance suite as a weekly bench check, not a final-stage gate, so eye-margin regressions surface in days rather than at the accredited test lab.
• Pick low-capacitance ESD protection. TVS arrays under 0.5 pF per line (with IEC 61000-4-2 level 4 robustness) keep the eye open while passing the CE ESD immunity test.
• Plan for USB4 v2 and USB-PD 3.2 today. Even on a Gen 2 design, choose connectors, controllers and laminates compatible with 80 Gbit/s and 240 W so the next product cycle reuses the platform with minimal rework.

Related articles

• PCI Express bus: performance and evolution - another point-to-point high-speed bus
• I2C bus protocol - low-speed companion bus on every embedded design
• SPI bus protocol - serial bus for sensors and memory
• LVDS / OpenLDI video format - high-speed differential video link
• AESTECHNO hardware design - methodology from prototype to production

FAQ: USB 3

What is the difference between USB 3.0, USB 3.1 and USB 3.2?
USB 3.0 delivers up to 5 Gbit/s (SuperSpeed). USB 3.1 doubles that to 10 Gbit/s (SuperSpeed+). USB 3.2 reaches 20 Gbit/s by using two differential lane pairs simultaneously (2×2 mode). Watch out for the renaming: USB 3.1 Gen 1 = USB 3.0 (5 Gbit/s), USB 3.2 Gen 2 = USB 3.1 (10 Gbit/s). Always check the actual specification, not just the marketing label.

What is 8b/10b vs 128b/132b coding in USB?
The line coding sets transmission efficiency. USB 3.0 Gen 1 uses 8b/10b: for 8 data bits, 10 bits are sent (80% efficient, useful rate 4 Gbit/s out of 5 Gbit/s). USB 3.2 Gen 2 uses 128b/132b: 128 data bits over 132 transmitted (97% efficient, useful rate 1,212 MB/s out of 10 Gbit/s). The 128b/132b coding cuts overhead and lifts real-world performance.

Is USB 3 backward-compatible with USB 2.0?
Yes, fully. A USB 3.x device works on a USB 2.0 port (capped at the USB 2.0 speed of 480 Mbit/s). Conversely, a USB 2.0 device works on a USB 3.x port. Backward compatibility is provided by the extra contacts on the USB 3 connector (the blue tongue) which do not interfere with the existing USB 2.0 contacts.

What are the PCB design constraints for USB 3?
USB 3 calls for 90 ohm differential routing on the SuperSpeed pairs (TX+/TX-, RX+/RX-), kept apart from the USB 2.0 D+/D- signals. Key constraints: matched intra-pair lengths (±5 mils), no stubs, minimised vias, continuous ground reference, short routing (< 15 cm on PCB to limit attenuation). For USB 3.2 Gen 2×2 (20 Gbit/s), signal-integrity demands are even stricter.

Does USB-C automatically support USB 3?
No. USB-C is a physical connector format, not a protocol version. A USB-C cable or port can support: USB 2.0 only (480 Mbit/s), USB 3.2 Gen 1 (5 Gbit/s), USB 3.2 Gen 2 (10 Gbit/s), USB 3.2 Gen 2×2 (20 Gbit/s), USB4 (40 Gbit/s), or Thunderbolt 3/4. Always check the cable and port specifications - not all USB-C is equivalent. The USB-C connector also supports the Power Delivery protocol, so for an industrial product powered through USB-C the USB-C PD specifics must be designed in carefully.