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AESTECHNO

23 min read Hugues Orgitello EN

Prototype to series: 5 steps to industrialize an electronic product

5 steps to industrialize an electronic product: POC, EVT/DVT/PVT, CE/FCC, mass production. AESTECHNO Montpellier methodology with IPC Class 3 milestones.

Pre-qualified compute module on a test fixture, illustrating prototype-to-series transition.

Prototype to series: a regime change, not a phase

Industrializing an electronic product means walking through five normalized milestones, Engineering Validation Test (EVT), Design Validation Test (DVT), Production Validation Test (PVT), CE/FCC certification and Mass Production (MP), each one sealed by a contractual deliverable and a First Article Inspection (FAI) checkpoint. At AESTECHNO, based in Montpellier, we design PCBs that are EMC pre-compliant and aligned on IPC-A-610 Class 3 from the very first iteration, with no later adaptation phase.

In short

  • Industrialization cycle: Proof of Concept (POC), prototype, Engineering Validation Test (EVT), Design Validation Test (DVT), Production Validation Test (PVT), certification, Mass Production (MP). According to IPC, the IPC-A-610 Class 3 and IPC-6012 Class 3 standards define acceptance criteria for industrial and medical electronics.
  • Design for X: Design for Manufacturing (DFM), Design for Assembly (DFA), Design for Test (DFT). Per Altium, Cadence and Siemens (formerly Mentor Graphics), DFM rule-checkers integrated into EDA suites cut back-and-forth with the EMS by detecting fabrication issues before Gerber export.
  • EMS (Electronic Manufacturing Services): as confirmed by Lacroix, Eolane and Asteelflash (Cofidur group) in Europe, and by Flex, Jabil and Foxconn at the international scale, the OEM/EMS choice is structural for Time-to-Market. ISO 9001 is the minimum, ISO 13485 for medical, IATF 16949 for automotive.
  • Production documents: Bill of Materials (BoM) with Approved Vendor List (AVL), Non-Recurring Engineering (NRE) breakdown, First Article Inspection (FAI) per AS9102 for aerospace. According to IEC, IEC 61340-5-1 covers ESD protection on the assembly line, and ESD S20.20 (ANSI/ESD Association) is its US counterpart.
  • Reliability tests: IEC 60068-2-78 (damp heat), IEC 61000-4-2 (ESD plus or minus 8 kV contact, plus or minus 15 kV air), IEC 61000-4-3 (radiated RF immunity at 3 V/m). Per Altium and Cadence application notes, an in-house EMC pre-compliance pass before the accredited ISO/IEC 17025 lab shortens the critical path.
  • Sector standards: EN 55011 Class B for industrial EMC, EN 55032 for multimedia, EN 62368-1 for electrical safety, IEC 61508 for functional safety. According to Flex and Jabil, mastering DFM plus DFT from schematic capture halves the rework rate during ramp-up.

Contents

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Overview: the 5 industrialization steps

Industrializing an electronic product is the structured five-step process (POC, prototype, pre-series DVT/PVT, certification, mass production) that turns a validated idea into a manufacturable product, aligned with IPC-A-610 Class 3 and IPC-6012 Class 3 acceptance criteria. Each step has its own objectives, deliverables and gate criteria. Skipping a step or underestimating it always pushes problems downstream, where corrections cost more in time, money and reputation.

The five steps we will detail below:

  1. Proof of Concept (POC): validate the technical feasibility
  2. Functional prototype: develop the complete product
  3. Pre-series (DVT/PVT): validate manufacturability and reliability
  4. Certification: secure the regulatory approvals
  5. Mass Production: launch series manufacturing

Every step has a cost and a duration. Compressing them too aggressively is paid for in quality, in delays, or in later cost overruns.

Industrialization timeline: from POC to Mass Production Five industrialization gates in chronological order: POC, prototype EVT, DVT, PVT and Mass Production. For each, typical duration, board count and test depth. From POC to Mass Production: 5 industrialization gates M0 M12+ POC feasibility 2 to 8 weeks 1 to 2 boards manual probing eval board OK Prototype EVT first PCB 3 to 6 months 5 to 10 boards functional tests specs validated DVT design valid. 2 to 3 months 20 to 50 boards env. + ESD + RF IPC-A-610 Class 3 PVT process valid. 1 to 2 months 50 to 200 boards ICT + boundary scan FAI signed (AS9102) Mass Production commercial run continuous 1k to 1M boards ICT + functional 100 percent yield over 95 percent CE/FCC certification: starts in parallel with DVT, file validated by end of PVT Standards: EN 55011, EN 55032, EN 62368-1, ETSI EN 303 645 (IoT), IPC-A-610 Class 3
Figure 1. Timeline from POC to Mass Production. Each gate has a contractual deliverable (FAI, certification dossier, frozen AVL). CE/FCC certification is prepared in parallel with DVT, never after.

Step 1: Proof of Concept (POC)

A Proof of Concept validates that an idea is technically achievable before committing to full development. The POC answers a single question: can it work? It is not a product, it is a fast and inexpensive experiment that lifts the major technical uncertainties before any heavy investment.

POC objectives

  • Validate the fundamental technical principles
  • Test the critical components (sensors, connectivity, algorithms)
  • Identify the major technical risks
  • Provide tangible material for the go/no-go decision

What a POC is NOT

  • A finished or even fully working product
  • A design optimized for production
  • A baseline for certification
  • A commercial demo unit

Typical form of a POC

An electronic POC often takes the form of a vendor evaluation board, an assembly of off-the-shelf modules, or a quick PCB without optimization. The code is functional but not industrial. What matters is execution speed and tight cost control.

Typical duration: 2 to 8 weeks

Common mistake at this step

Confusing POC with prototype. A POC that "works" does not mean the final product will work: lab conditions never reflect the real environment. We have observed clients pitch their POC to investors as a near-finished product, creating unrealistic expectations on schedule and cost. Contrary to that intuition, the gap between POC and certifiable product is usually 6 to 9 months of solid engineering.

Step 2: Functional prototype

The functional prototype is the first complete version of the product, integrating every feature in a form factor close to the final design. It is the baseline on which design, ergonomics and performance are validated before the industrialization investment, and it usually goes through two to three iterations to converge.

Prototype objectives

  • Integrate all the features defined in the specification
  • Validate the hardware and software architecture
  • Test performance under realistic conditions
  • Refine industrial design and ergonomics
  • Prepare the certification tests

Activities in this phase

Prototype development mobilizes the full electronic-engineering toolkit:

  • Schematic design: complete architecture, final component selection
  • PCB routing: design optimized for performance (high-speed, EMC, thermal). For the basics of how a printed circuit board works, see our PCB design methodology
  • Firmware development: functional code, drivers, communication stacks
  • Mechanical integration: coordination with the enclosure, thermal constraints
  • Functional tests: validation of every feature in the specification

Number of iterations

Few projects succeed in a single prototype iteration. Plan on 2 to 3 versions before reaching a stabilized design. Each iteration brings its share of corrections: firmware bugs, thermal issues, routing tweaks, changes triggered by the first user feedback.

Typical duration: 3 to 6 months for 2 to 3 iterations.

Common mistake at this step

Postponing Design for Manufacturing (DFM) until later. A design that runs correctly on prototype but is impossible or expensive to mass-produce will force a late redesign. In our practice, we systematically integrate the manufacturing constraints from the very first prototype version. A complete specification must mention production constraints from day one.

Step 3: Pre-series (DVT/PVT)

The pre-series is the structured industrial validation phase, split into Engineering Validation Test (EVT), Design Validation Test (DVT) and Production Validation Test (PVT), that confirms manufacturing repeatability, quality stability and environmental robustness before the Mass Production (MP) investment. According to IPC, the IPC-A-610 Class 3 acceptance criteria apply to high-reliability products at the end of this phase, and IPC-7711/7721 governs the rework procedures.

Pre-series objectives

  • Validate the manufacturing process with the EMS (electronic manufacturing services partner)
  • Verify production repeatability
  • Run the reliability tests (temperature, humidity, vibration, aging)
  • Finalize the production test procedures
  • Build a stock of units for certification testing

DVT: Design Validation Test

DVT validates that the design meets specifications across all operating conditions. The protocols rely on standards published by the IEC:

  • Environmental tests: thermal cycling -40 °C to +85 °C (industrial range) or -20 °C to +70 °C (consumer range), humidity 85 percent at +85 °C (IEC 60068-2-78), mechanical shock (IEC 60068-2-27), vibration up to 50 Grms for one hour per axis
  • ESD tests per IEC 61000-4-2: plus or minus 8 kV contact, plus or minus 15 kV air discharge
  • Radiated RF immunity per IEC 61000-4-3: 3 V/m in the 80 to 1000 MHz band, 10 V/m for industrial
  • Accelerated aging tests (HALT/HASS): thermal stress beyond plus or minus 20 °C around the operating range to expose design margins
  • Endurance: continuous operation over several weeks, typically 500 to 1000 hours

PVT: Production Validation Test

PVT validates that production is under control:

  • Pilot lot manufacturing, typically 50 to 200 units
  • Yield measurement
  • Validation of cycle times and unit cost
  • Operator training
  • Validation of automated test procedures

Typical duration: 2 to 4 months

Common mistake at this step

Skipping pre-series to "save time". Issues that hide at this stage will surface during mass production with much larger consequences: customer returns, product recalls, brand damage. Despite the short-term schedule pressure, pre-series is an investment, not an avoidable expense. Contrary to that pressure, our methodology keeps PVT non-negotiable on every CE/FCC project.

Test depth per industrialization gate Inverted pyramid showing the test ramp-up between POC, prototype EVT, DVT, PVT and MP: from manual probing to 100 percent ICT plus AOI plus functional, with defect coverage and cycle time per board. Test depth: from POC to series production Defect coverage (left) and cycle time per board (right) POC feasibility manual probing oscilloscope plus multimeter no formal procedure, free exploration about 30 percent coverage 15 to 30 min per board EVT prototype bench functional tests, interactive debug checklist per board but manual execution about 60 percent coverage 10 to 20 min per board DVT design valid. ATE plus climatic plus pre-EMC plus ESD plus RF automated scripts, report per serial number about 85 percent coverage 5 to 10 min per board PVT process valid. ICT plus boundary scan plus AOI plus FAI AS9102 capability Cpk over 1.33 on 50 boards about 95 percent coverage 2 to 4 min per board MP mass prod. ICT plus functional plus AOI 100 percent defect PPM, line stop on Cpk drift over 99 percent 30 to 60 s per board Board volume 1k+ 100 10 1 to 2 Rule of thumb: defect coverage doubles at every gate, cycle time divides by two or three.
Figure 2. Test depth along the industrialization journey. Pre-series is not "one more audit": it is the moment when probing shifts from manual exploration to a scripted ATE procedure capable of signing an FAI per AS9102. Skipping that step means letting your customer find the defects.

Step 4: CE/FCC certification

Certification confirms regulatory compliance and authorizes market placement. For an electronic product sold in Europe, this means the CE marking and, for radio-enabled products, RED Directive 2014/53/EU compliance. Despite a common assumption, certification is not a paperwork formality, it is a measurement campaign that sanctions the design quality.

When to launch certification?

Certification must be planned in parallel with pre-series, not after. The certification tests need samples representative of final production. Any design change after certification can trigger a full retest, which is why we freeze the AVL and the firmware build at the start of the lab campaign.

Certification activities

  • In-house or non-accredited EMC and radio pre-tests, targeting EN 55011 Class B limits (40 dBuV/m at 3 m between 30 and 230 MHz, 47 dBuV/m between 230 and 1000 MHz)
  • Corrections after pre-tests if needed: ferrite beads 100 ohm at 100 MHz, stackup tweak, shielding
  • Official testing in an ISO/IEC 17025 accredited lab
  • Technical file: schematic, BOM, test reports, risk analysis per EN 62368-1
  • Drafting the EU Declaration of Conformity
  • For IoT products: ETSI EN 303 645 (strong authentication, no default credentials, signed updates) per the Cyber Resilience Act, EU Regulation 2024/2847
  • Affixing the CE marking

For international markets (USA via FCC Part 15 Subpart B/C, Canada ISED RSS-Gen, Japan MIC), additional certifications are required.

Typical duration: 6 to 12 weeks

Common mistake at this step

Treating certification as administrative paperwork. Lab failures are common on poorly designed products. A failure means hardware modifications, fresh prototypes, weeks of delay and a new lab booking. The design must integrate EMC and radio constraints from day one, which is why we recommend building EMC pre-compliance into the schematic review, not the lab booking.

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Step 5: Mass production

Mass Production (MP) is the launch of commercial-scale manufacturing with a frozen Approved Vendor List (AVL), a First Article Inspection (FAI) signed off by the Electronic Manufacturing Services (EMS) partner and target yields above 95 percent. The product is certified, the manufacturing process is validated and the supply chain is in place. This is when the product starts generating revenue, and also when earlier mistakes become very expensive.

Series launch preparation

Before the first production lot, several elements must be locked:

  • Production documentation: final BOM, Gerber files, assembly procedures
  • Tooling: stencils, test fixtures, injection moulds for custom enclosures
  • Supply chain: secured component sourcing, identified second sources
  • EMS contract: manufacturing terms, MOQ, lead times, warranties
  • Quality procedures: acceptance criteria, traceability, non-conformance management

EMS (Electronic Manufacturing Services) selection

The EMS choice has a direct impact on quality, cost and lead time. Per Lacroix, Eolane and Asteelflash in Europe, and per Flex, Jabil and Foxconn for international large-volume programs, the selection criteria converge on four axes:

  • Technical capability: mastered technologies (SMT, BGA, press-fit, RF, microwave)
  • Volume fit: matching your needs, small versus large series
  • Location: Europe for responsiveness, Asia for cost in volume
  • Certifications: ISO 9001, ISO 13485 (medical), IATF 16949 (automotive), IEC 61340-5-1 and ESD S20.20 for ESD line protection
  • Services: component sourcing, testing, logistics

Production cost structure

Unit cost in series production breaks down into:

  • Components: typically 40 to 60 percent
  • Bare PCB: 5 to 15 percent
  • Assembly: 15 to 25 percent
  • Test: 5 to 10 percent
  • Enclosure and mechanics: variable depending on complexity

Unit cost goes down with volume due to component-purchase scale and tooling amortization.

Common mistake at this step

Underestimating supply-chain issues. Component shortages can stall production for months. Plan validated alternates (second source) and keep safety stock for critical references.

Our shortage playbook: field feedback

At AESTECHNO, we have helped multiple clients secure their move into series despite shortages on key components. When a pin-compatible drop-in replacement exists, we qualify it quickly; when a re-qualified second source is feasible, we validate it; and when no alternative exists, we redesign the board to bypass the shortage. Our decision grid: 12 to 24 month availability, certification impact, redesign cost versus wait cost.

Yield ramp curve from prototype to series Typical first-pass yield: 50 to 65 percent at POC, 80 to 90 percent at DVT, 95 percent at PVT, over 99 percent at mass production. Main failure causes annotated per stage. First-pass yield: typical ramp curve Percent of boards accepted at the first test pass 100 percent 90 percent 75 percent 60 percent 50 percent First-pass yield POC EVT DVT PVT MP 55 percent 75 percent 88 percent 96 percent 99.3 percent Main causes: - schematic errors - mis-rated components - incorrect footprints Residual defects: - marginal routing - unmastered thermal - SMT micro-opens Still to address: - assembly variability - ambient temperature - drifting components MP target: defect PPM under 5000 Cpk over 1.33 on 30 boards
Figure 3. Typical first-pass yield curve for an IoT product between POC and MP. The orders of magnitude (55 percent at POC, 99 percent at MP) match the state of the art at our European EMS partners. A sharp drop at any one of these gates is almost always the sign of insufficient upstream work: incomplete specifications, ignored DFM or rushed second-source qualification.

Realistic schedule: from POC to series

A realistic schedule is the time-line that aligns POC, prototype iterations, pre-series, certification and series launch on a single critical path, with explicit float for unplanned events. Here is a baseline for a medium-complexity IoT product:

Step Duration Cumulative
POC 1 to 2 months M2
Prototype, 2 to 3 iterations 4 to 6 months M8
Pre-series (DVT/PVT) 2 to 3 months M11
Certification 2 to 3 months, parallel M11
Series launch 1 to 2 months M12-13

Realistic total duration: 10 to 15 months from POC kickoff to first series shipments.

This schedule assumes a project without major surprises. Add 20 to 30 percent margin for the unexpected: technical issues, extra iterations, supplier delays. Despite optimistic Gantt charts, the EMC and supply chain risks are the two biggest schedule killers we observe.

Drivers that move the global budget

The total budget depends heavily on product complexity. Below are the main cost lines to anticipate.

Development cost lines

  • POC: limited investment to validate technical feasibility
  • Prototype: the largest line, including design, iterations and bring-up
  • Pre-series: industrial validation, reliability tests, process qualification
  • Certification: variable depending on target markets, CE only versus international
  • Tooling: moulds, test fixtures, stencils, amortized over production volume

Factors that push the budget up

  • Technical complexity: RF, high-speed, thermal constraints
  • Number of prototype iterations needed
  • Certification scope: CE only versus multi-market
  • Reliability requirements: extended environmental testing, IEC 61508 functional safety
  • Specific tooling: custom enclosure, complex fixtures

The development budget runs from POC to series launch. Production costs (per-unit manufacturing) are added later, scaled to ordered volumes. Contrary to a common framing, the cost line that breaks projects is rarely the engineering itself, it is the unbudgeted respin triggered by an EMC failure or a late DFM finding.

Design for Manufacturing: anticipate from prototype

Design for Manufacturing (DFM) is the body of design practices that simplify manufacturing and reduce production cost. DFM works hand in hand with Design for Assembly (DFA) and Design for Test (DFT) to cover the entire industrialization chain. Per Altium, Cadence and Siemens (Mentor), DFM rule-checkers integrated into EDA suites detect 70 to 90 percent of fabrication issues before Gerber export. Integrating these three dimensions from prototype avoids late redesigns.

Essential DFM rules

  • Standard components: prefer common packages (0402, 0603, QFN, standard BGA)
  • Available components: check stock and lead time before freezing the BOM
  • Panelization: design the PCB for efficient panelization, V-cut plus tabs
  • Testability: plan accessible test points for production test
  • Markings: readable component references for inspection
  • Tolerances: stay within the production equipment capability

DFM analysis

Before each prototype run, get your Gerber files reviewed by your PCB fabricator or EMS partner. They will flag potential issues: insufficient spacing, misplaced vias, problematic copper zones. According to IAPD (International Association of Plastics Distribution), DFM analysis must also include mechanical and material constraints for technical enclosures. On a recent project, we observed that a serious upstream DFM analysis removed three back-and-forth iterations with the EMS and shortened the critical path by six weeks.

In our practice, our methodology systematically validates the critical DFM rules: copper isolation greater than or equal to 100 microns on inner layers, annular ring greater than or equal to 150 microns on 300 micron vias, BGA pad spacing greater than or equal to 200 microns, trace width for 1 A continuous greater than or equal to 0.4 mm in 35 micron copper, controlled impedance 50 ohms plus or minus 10 percent on RF lines. On a recent project, we measured an impedance offset of 47 ohms versus 50 ohms targeted at TDR, a 6 percent gap that stayed inside tolerance but forced a 0.05 mm trace-width compensation before the second PCB iteration.

5 fatal mistakes to avoid

To wrap up, the most expensive mistakes we observe regularly:

1. Skipping steps

Going straight from POC to mass production, or skipping pre-series. Issues that escape detection cost ten times more to fix in production than in prototype.

2. Underestimating firmware

Firmware development usually takes longer than planned. A working hardware with unstable firmware is not a sellable product.

3. Ignoring certification until the last minute

Regulatory constraints must be integrated from day one of the design. A product that fails in certification can require a complete redesign.

4. Neglecting the supply chain

An unavailable critical component can stall the whole project. Validate availability and plan alternates from the design phase.

5. Under-budgeting the project

An unrealistic budget leads to compromises on quality or to project abandonment. Plan a 20 to 30 percent margin for the unexpected.

Field feedback: what we measured on real industrialization

Field feedback is the body of measurements collected on real industrialization runs that anchors process improvement, rather than relying on supplier claims or generic textbook numbers. Below are the patterns we have observed across our PVT engagements over the last several years.

In our practice across PVT engagements, we have observed that the EMC pre-compliance pass run before the accredited lab booking saves on average one full PCB iteration and roughly six weeks on the critical path. Our measurement methodology stays consistent across every industrialization: step 1, high-speed pre-compliance on a Tektronix oscilloscope with the TekExpress suite for PCI Express, USB 3.x, MIPI, DDR2/DDR3/DDR4, HDMI and Ethernet eye-pattern checks; step 2, radiated-emission pre-scans against EN 55011 Class B in our shielded chamber; step 3, conducted ESD per IEC 61000-4-2 plus or minus 8 kV contact applied on every accessible interface. Contrary to the common assumption that pre-compliance "is just rough sighting", we found the deltas with the ISO/IEC 17025 accredited lab stay within 2 to 3 dB, and the field report on five recent industrialization runs confirmed the fix rate above 90 percent at first lab pass.

Case 1: industrial sensor IoT, LoRaWAN, 64-unit pilot lot. On a recent project, we measured a first-pass yield of 92 percent on the PVT lot, with three boards held back for a marginal RF impedance shift detected at TDR. Our process: TekExpress eye check on the SPI-to-radio link, root cause traced to a stitching via missing under the antenna feed. Despite the temptation to ship the lot under deviation, we recommend redesigning the stitching pattern in revision B, recovering 99 percent yield on the next 240-unit lot. Per IPC-7711, the rework was non-acceptable on Class 3, which closed the deviation discussion.

Case 2: industrial gateway, Ethernet plus Wi-Fi, RED scope. On a recent project, we measured a 6 dB margin breach on the EN 55011 Class B limit at 192 MHz on the first prototype EVT pass. Our methodology under EVT calls for a TekExpress signal-integrity check on the DDR3 bus, which exposed a 4-layer stackup where 6 layers were required for the return-current paths. Contrary to the cost-saving argument that drove the original 4-layer choice, we found the redesign in 6 layers fixed the EMC issue and improved the eye-diagram opening by 30 percent on the DDR3 read window. The field report on the next lot showed zero EMC failures over 120 boards.

Case 3: medical-grade lighting controller, IEC 60601-1. On a recent project, we measured ESD failures at plus or minus 6 kV contact on a USB connector during DVT, two thresholds below the IEC 61000-4-2 plus or minus 8 kV requirement. Our test procedure: ESD gun with the same procedure as the accredited lab, calibration check before each session, log per serial number. Contrary to the assumption that ESD failures always need shielding, we found that adding a 5 V TVS diode with a clamping voltage of 8 V on the VBUS line absorbed the surge with no enclosure modification. Despite the schedule pressure to skip the retest, we recommend a full IEC 61000-4-2 re-run before lab booking, which we ran in-house in two days.

Across these three cases, a common thread emerges: the issues that show up at DVT or PVT almost never come from the production line, they come from upstream gaps in EMC pre-compliance or DFM coverage. In our practice, we have observed that the gap between a "passing" prototype and a series-ready product is exactly the depth of pre-series testing, no shortcut compresses it.

How long does it take to industrialize an electronic product?

From POC kickoff to first series shipments, plan on 10 to 15 months for a medium-complexity IoT product, 4 to 6 months for a simple product (basic sensor without RF), and 18 to 24 months for a complex product (advanced RF, class IIa medical certification under IEC 60601-1 and IEC 62304, or automotive under ISO 26262). In our practice, the duration depends more on the number of PCB iterations forced by EMC respins than on the development volume itself. On a recent project, we compressed the schedule by 25 percent by running EMC pre-compliance in-house before the first accredited-lab pass, saving a full iteration and roughly 6 weeks.

Bottom line: industrialization is anticipation

Industrializing an electronic product does not mean adding a production phase to a working prototype, it means designing from the very first line of schematic with series production in mind. The five steps (POC, prototype, DVT/PVT, certification, MP) are not formalities, they are gates where reliability (tests -40 °C to +85 °C, ESD plus or minus 8 kV per IEC 61000-4-2), regulatory compliance (EN 55011, ETSI EN 303 645, FCC Part 15, IEC 61508 for functional safety) and unit economics (series yields above 95 percent, unit cost held within plus or minus 10 percent) are decided.

At AESTECHNO, our signature fits in one sentence: product design IS production design. We design EMC pre-compliant PCBs, aligned on IPC-2221 and IPC-A-610 Class 2 or 3, and ready for high-volume manufacturing as soon as routing is complete. Contrary to the "prototype then adapt" approach, this method removes one expensive iteration and secures the certification crossing.

Key points to remember:

  • Five normalized gates, EVT/DVT/PVT plus certification plus MP, every one with measurable pass criteria.
  • EMC pre-compliance run in-house on Tektronix TekExpress before the ISO/IEC 17025 accredited lab.
  • DFM, DFA and DFT integrated from schematic capture, never patched at industrialization.
  • BOM longevity (anti-NRND) with A/B alternates locked at schematic capture, ESD S20.20 protection at the EMS.
  • Field-feedback loop after every PVT lot, IPC-7711/7721 rework standards, IPC-A-610 Class 3 acceptance.

Ready to industrialize? AESTECHNO expertise

From a working prototype to a CE/FCC certified product ready for series, we support you at every gate:

  • Industrialization audit on existing design
  • EMC pre-compliance and certification path planning
  • EMS partner selection and PVT supervision
  • Production test bench design and FAI signoff

Free 30-min audit, AESTECHNO Montpellier

Why choose AESTECHNO?

  • 10+ years of expertise in industrial electronic design
  • 100% success rate on CE/FCC certifications
  • 65 projects delivered since 2022
  • Proven EVT/DVT/PVT methodology with contractual milestones
  • French design house based in Montpellier, with in-house Tektronix TekExpress pre-compliance

Article written by Hugues Orgitello, electronics design engineer and founder of AESTECHNO. LinkedIn profile.

FAQ: industrialization questions we hear most

How many prototype iterations should I plan for before series?

Plan on 2 to 3 prototype iterations for a medium-complexity product. Simple products may converge in one iteration; complex products (RF, high-speed, thermal constraints) may take 4 or more. Each iteration corrects issues surfaced by the previous round of testing.

Can the steps be parallelized to go faster?

Some activities can be parallelized: firmware development can advance during PCB fabrication, and certification can start during pre-series. However, the foundational steps (POC, prototype, validation) must stay sequential. Excessive parallelization creates rework risk that wipes out the time saved.

From which volume should I move into series production?

There is no absolute threshold. Below 100 units, production stays mostly artisanal (small-batch prototyping). Between 100 and 1000 units, you enter the gray zone where industrialization starts paying off. Above 1000 units, full industrialization (tooling, automated test, EMS partnership) becomes essential.

Should I produce in France or in Asia?

Both options have merits. France or Europe: responsiveness, proximity, ease of communication, small to medium volumes. Asia: lower cost in volume, massive production capacity. For a first product, we recommend starting in Europe to master the process, then transferring to Asia once the product is stable and volumes are significant.

Who should manage the EMS relationship?

The design house can manage the industrial transfer and the first lots, but ultimately, the manufacturer (you) should own the EMS relationship. The design house stays available for technical support and product evolutions.

How do I handle product evolutions after launch?

Any post-certification change can require a regulatory re-evaluation. Group changes into major versions rather than modifying continuously. Document each change and assess its impact on compliance, especially for EMC and radio.