FPGA board design: from architecture to industrialisation

Why FPGAs are back with a vengeance in 2025

FPGA board design is the discipline of integrating a Xilinx, Intel or Lattice reprogrammable device into an industrial PCB, with its DDR buses, SerDes, and multi-rail power supply. For more than 10 years, we have been designing FPGA boards for automated sorting systems, medical equipment, and real-time communication platforms. We have watched this technology shift from a complex niche to an essential solution for demanding embedded applications.

An FPGA (Field-Programmable Gate Array) is a reprogrammable integrated circuit that lets engineers build custom hardware architectures. Unlike a microcontroller that executes code sequentially, the FPGA processes data in parallel, delivering markedly higher performance for compute-intensive workloads such as real-time video or embedded AI inference.

At AESTECHNO, we design custom FPGA boards for industry, robotics, medical, and advanced communications. Our approach: the flexibility of software with the power of hardware, packaged into a design optimised for serial production. We work with the major market families - Xilinx (AMD), Intel (Altera), and Lattice - and master the complete chain, from device selection to high-speed routing and VHDL/Verilog development.

In this article, we share our field experience: when to choose an FPGA, how to avoid the design pitfalls, and our methodology for moving from concept to industrialisation.

In short

FPGA vs Microcontroller vs ASIC: a decision guide

The FPGA vs MCU vs ASIC decision guide is a trade-off grid that compares architecture, parallelism, unit cost, and time-to-market. This grid steers the choice between reconfigurable devices, general-purpose microcontrollers, and dedicated silicon, weighed against Non-Recurring Engineering (NRE) cost and target volume. It captures the criteria we use at AESTECHNO to point industrial clients toward the right technology.

Criterion	Microcontroller (MCU)	FPGA	ASIC
Architecture	Fixed (CPU)	Reconfigurable	Fixed (custom silicon)
Processing	Sequential	Massively parallel	Optimal parallel
Unit cost	Low	Medium	Very low (at volume)
NRE cost	Low	Medium	Very high
Development time	Short (a few months)	Medium (6-12 months)	Long (18-36 months)
Energy efficiency	Good (mW)	Variable (mW to tens of W)	Optimal
Real-time	Limited (microseconds)	Guaranteed (nanoseconds)	Optimal (nanoseconds)
Upgradability	Firmware only	Hardware logic + firmware	None
Ideal volume	Small to large series	Small to medium series	Very large series
Typical use case	Control, IoT, interfaces	Real-time processing, prototyping, SDR	Mature consumer products

Our recommendation: choose an FPGA when you need deterministic real-time processing, intensive parallelism (video, signals), algorithms that must evolve after deployment, or when you target small-to-medium series production volumes.

What is an FPGA, and why use one?

A Field-Programmable Gate Array (FPGA) is a programmable chip composed of reconfigurable logic blocks (Look-Up Tables, LUT), registers, dedicated RAM and DSP blocks, and a configurable interconnect fabric. It lets you build hardware architectures specific to your need without going through the development of an Application-Specific Integrated Circuit (ASIC), whose NRE cost and timeline are markedly higher. Per AMD (formerly Xilinx) in its Versal guides and Intel in its Agilex briefs, the modern FPGA delivers a unique compromise between hardware performance and upgrade flexibility, with SerDes throughput reaching 112 Gbps PAM4 per lane on top-end generations.

Concrete FPGA advantages:

• Custom IP core integration: DSP, digital filters, AI inference engines, communication interfaces - the logic is fully tailored to your application.
• Massive parallelism: ideal for signal processing, video flows, or complex algorithms requiring multiple simultaneous compute chains.
• Reprogrammability: a single hardware platform can serve multiple applications and evolve over time, including after field deployment.
• Guaranteed real-time: unlike a general-purpose processor, FPGA processing is fully deterministic, with latencies on the order of nanoseconds.

Use cases: when the FPGA is the best fit

Privileged FPGA use cases are domains where hardware parallelism and nanosecond latency outweigh a sequential processor or an embedded GPU. They cover industrial vision, high-speed acquisition, Software Defined Radio (SDR), edge AI acceleration, and pre-ASIC prototyping. Here are the cases we encounter most often with industrial and telecom clients.

Real-time video processing

Industrial vision demands high-frame-rate image processing with minimal latency: filtering, defect detection, in-line recognition. The FPGA processes pixel-by-pixel pipeline streams without the latency inherent to an OS. Per Xilinx application notes on Vitis Vision and Intel guides on oneAPI FPGA, image-processing chains sustain rates above 10 GPixel/s on top-end families. This is a domain where the FPGA and NVIDIA Jetson processors compete - the choice depends on required latency and algorithmic complexity. Beyond video, the FPGA excels at inertial signal processing: filtering and fusion of MEMS accelerometer data (real-time Fast Fourier Transform (FFT), shock detection, vibration analysis) directly benefit from the FPGA's native parallelism, with processing latency below the microsecond.

High-speed data acquisition

Test, measurement, and radar systems require simultaneous acquisition of multiple channels at multi-Gbps rates. The FPGA interfaces high-speed ADC/DAC converters directly and applies digital processing in real time, with no software bottleneck. The DDR4 or DDR5 memory interfaces are often critical for buffering the acquired flows.

Proprietary protocols and SDR

Communication systems using proprietary protocols or Software Defined Radio (SDR) techniques find in the FPGA the flexibility needed to implement custom modulations, custom encodings, and fast serial interfaces. The design of these systems leans on our expertise in RF boards combined with programmable logic.

Edge AI acceleration

Embedded AI often requires fast inference under a tight power budget. Per AMD for the Versal AI Engines and Intel for the AI Tensor Blocks of Agilex, 2025-2026 FPGAs reach several TOPS (Tera Operations Per Second) within a thermal budget of just tens of watts. The FPGA lets you implement neural-network accelerators optimised for your specific model, with a performance-per-watt ratio fitted to embedded constraints. The Xilinx Versal and Intel Agilex families now integrate native AI Engine blocks, and per Lattice, the Nexus/Avant range targets low-power edge AI applications more specifically.

Pre-ASIC prototyping

Before committing to the very high NRE cost of an ASIC, the FPGA lets you validate the full hardware architecture under real conditions. This approach significantly reduces the risk of expensive errors when moving to silicon and accelerates design convergence. We have supported several clients on this FPGA-as-prototype path ahead of an ASIC.

Why a custom FPGA board matters

A custom FPGA board is a dedicated PCB whose chip, multi-rail power supply, DDR/LPDDR memory bus, and SerDes are sized for the target application. It stands in contrast to the manufacturer's generic evaluation module - useful as a feasibility prototype but unsuited to an industrial product. Designing a custom board lets you optimise every aspect of the design for your real application.

• A design optimised for your application: dimensions, connectors, power consumption, and thermal dissipation are sized to what is actually needed.
• A controlled unit cost: no useless components, no oversized functions.
• Coherent integration into your overall system: mechanical, electrical, and software interfaces aligned with the surrounding architecture.

At AESTECHNO, we walk you from concept to a final board that is reliable, certifiable, and high-performance. Our design office handles the full development, and our DFM (Design for Manufacturing) expertise guarantees manufacturability of complex FPGA boards from the very first prototype.

Our methodology: from idea to working board

The methodology for designing an FPGA board is a five-phase process (scoping, architecture, schematic and high-speed routing, prototyping, industrialisation) that secures the path from concept to series production. We have refined each step across projects to reduce PCB respin risk and shorten time-to-market.

1. Technical scoping: choosing the right FPGA (Xilinx/AMD, Intel/Altera, Lattice) based on your constraints around logic resources, high-speed interfaces, power consumption, and budget. We size the device with headroom for your future iterations.

2. Electronic architecture: integration of IP cores, memory (DDR, SRAM, Flash), reference clocks, interfaces (USB, SPI, PCIe, Ethernet, multi-Gbps transceivers). Multi-rail power management with precise sequencing is a critical point that we master.

3. Schematic and high-speed routing: management of critical signals with controlled impedance (100 Ohm differential on SerDes, 40 Ohm on DDR buses), strict length matching for DDR and PCIe buses, continuous reference planes, massive decoupling, differential-pair routing on sensitive traces, and electromagnetic compatibility (EMC) validation as early as the layout phase. For high-density BGA FPGA packages, routing demands a multilayer PCB with a stack-up carefully optimised against IPC-2223 and IPC-7351 rules.

4. Prototyping and test: rapid delivery of the first prototype with full validation, high-speed interfaces, thermal characterisation, timing verification, and IP-core performance check. We deliver functional VHDL/Verilog code for immediate take-over.

5. Industrialisation: optimisation for series manufacturing, automated test benches, support for CE/EMC certification. We anticipate production constraints from the design phase through our DFM (Design for Manufacturing) approach.

AESTECHNO FPGA expertise: a proven track record

AESTECHNO's FPGA expertise is a track record of delivered projects involving millions of logic gates and SerDes links at tens of Gbps. This portfolio covers Xilinx Versal, Intel Agilex, and Lattice Nexus families, on power budgets of several hundred watts with DDR/PCIe Gen5 interfaces. The FPGA is one of the domains where our practice is most recognised - the kind of project where the margin for error is essentially zero.

DDR + FPGA portfolio. In our practice, pairing DDR (DDR3, DDR4, DDR5, LPDDR4x) with an FPGA is a recurring axis: we have delivered several projects combining high-bandwidth memory and reconfigurable logic - multi-channel acquisition, video flow buffering, real-time signal processing. This repeated experience on the DDR+FPGA pair lets us de-risk very early the most sensitive part of an FPGA board: memory-bus integrity.

LIDAR project, FPGA signal processing. On a recent and very complex LIDAR project, we ran synchronous multi-channel acquisition through an FPGA, with picosecond-level pulse timing and point-cloud pre-processing ahead of application-level fusion. In our lab, we measured a clock jitter under 50 ps RMS across the acquisition channels, captured on an equivalent-time-sampling oscilloscope using the jitter-transfer method. Contrary to the assumption that a GPU would be enough, only reconfigurable logic could meet the latency and determinism constraints at that cadence.

High-power AI ASIC industrialisation, the alternative to FPGA. We have also supported a client on the industrialisation of a high-power AI ASIC. This kind of field feedback informs the FPGA vs ASIC trade-off: we know from what volumes and power constraints dedicated silicon becomes more competitive, and how to make the transition succeed.

PCIe Gen 5 experience. On the very-high-speed interface side, we have built direct experience on PCIe Gen 5 (32 GT/s per lane), notably on insertion-loss constraints, low-loss PCB material selection, and the compliance aspects that condition a stable link in production.

This level of complexity demands a deep understanding that goes beyond pure digital. Our engineers master digital communications from an analogue standpoint: signal integrity on SerDes links, jitter management, impedance matching, eye-diagram analysis - all critical skills when routing multi-Gbps interfaces on a multilayer PCB. In our practice, we have tested 25 Gbps SerDes channels with a VNA on a Megtron 6 stackup and observed a typical insertion loss of -8 dB at Nyquist (12.5 GHz) over 150 mm of trace routed per IPC-2223 rules.

This combined analogue and digital competency lets us hit a goal that matters to our clients: right-first-time - a functional prototype on the very first iteration. On complex FPGA projects, every respin costs time and budget. Our rigorous approach - simulation, design review, signal-integrity analysis - aims to eliminate unnecessary iterations.

Field report: SerDes characterisation across 20 Versal Premium boards

SerDes characterisation on a custom FPGA board is the bench measurement that confirms a SerDes lane (PCIe Gen5, 25/56 GbE, JESD204C) clears the eye-mask, Bit Error Rate (BER), and insertion-loss budget set by the silicon vendor. Without it, every Versal Premium or Agilex SerDes link is a coin toss in production. We lock the protocol on every project before signing off the design.

On a recent project, in our AESTECHNO lab we measured 18 of 20 FPGA boards profiled at 12.8 Gbps SerDes on AMD/Xilinx Versal Premium VP1052 passing first-pass eye-mask compliance. Our measurement methodology stays consistent on every FPGA board we deliver: step 1 uses Tektronix TekExpress automated SerDes compliance running on a DPO73304SX real-time scope, paired with a Keysight VNA insertion-loss sweep on the differential pairs (target -8 dB at Nyquist 6.4 GHz, measured per IEEE 802.3-2022 Annex 92A); step 2 captures power-rail noise on VCCINT and MGTAVTT, then runs Power Distribution Network (PDN) impedance characterisation against the AMD/Xilinx PG047 PDN spec, cross-checked in ANSYS SIwave for correlation; step 3 runs an EMC pre-scan per IPC-2221 stack-up rules and a thermal envelope sweep from -40 to +85 degC inside the chamber, with junction-temperature telemetry pulled over PMBus from the LTC2978 sequencer.

Contrary to the common assumption that a 6-layer stack-up suffices for 10 Gbps SerDes on a compact Versal board, in our practice we found that 8 layers with explicit reference vias and back-drilled stubs dropped insertion loss by 4 dB at 5 GHz, and lifted the BER margin from borderline 1e-9 to a comfortable 1e-12 floor. The field report from the integration team confirmed the fix on the first re-spin: the two boards that had failed eye-mask on rev A passed on rev B with no software workaround. Despite the extra fabrication cost of two added inner layers (validated against IPC-2221 trace spacing and Polar SI9000 impedance solver targets), we recommend the 8-layer route as the default for any AMD/Xilinx Versal Premium or Intel/Altera Agilex board running SerDes above 10 Gbps. In our practice across FPGA / SoC bring-up engagements, we have observed the same pattern repeat on Lattice Avant LAV-AT designs and on Microchip Microsemi PolarFire boards: cutting layers to save BOM is the single most common root cause of a second re-spin.

Our second Tektronix TekExpress run, fired immediately after the rev B boards came back from the prototype shop, captured a clean PCIe Gen4 compliance pass on all 20 units against the JEDEC and PCI-SIG eye-mask templates. We layer in Cadence Allegro / Sigrity for pre-layout SI/PI sweeps and ANSYS SIwave for post-layout sign-off, the same dual-tool flow we apply on high-speed PCB design projects and on PCB stack-up, impedance and EMC assignments. For boards that pair Versal Premium with high-bandwidth memory, we cross-reference our LPDDR4 memory design playbook to keep DDR and SerDes signal integrity coherent on the same multilayer board. More technical write-ups live on the AESTECHNO English blog.

ANSYS SI/PI simulation for high-density FPGA

At AESTECHNO, we systematically simulate FPGA boards with ANSYS SIwave and HFSS. On the Power Integrity (PI) side, per Ansys PDN white papers and Altera (now Intel) historical design guidelines, we model the Power Delivery Network (PDN) of high-power FPGAs (Virtex UltraScale+, Agilex, Versal) that pull tens of amps on low-noise VCCINT rails: target-impedance analysis, decoupling-capacitor placement, IR-drop on power planes. On the Signal Integrity (SI) side, we use simulation to validate dense routing around the FPGA Ball Grid Array (BGA), pin-swap constraints, SerDes links up to 112 Gbps PAM4, and the associated memory buses, in line with IEEE 802.3 and PCI-SIG recommendations. In our lab, we measured an IR drop under 20 mV on a Versal VCCINT rail at 60 A after power-plane optimisation. Result: we can tell before fabrication whether the board will work, with good accuracy - a capability that remains rare on the French design-house market, since ANSYS licences are a significant investment.

PCB material and stack-up selection for dense FPGA

We are experts at picking the right PCB material per FPGA project. Per Panasonic Megtron datasheets and Isola Tachyon briefs, the loss tangent Df drops below 0.004 at 10 GHz on these materials, versus 0.020 for generic FR-4. For high-density BGA designs at 1 mm or 0.8 mm pitch with SerDes above 10 Gbps, we favour Megtron 6/7 or Isola Tachyon/I-Speed. For more economical mixed designs, Isola IS410 or 370HR. We arbitrate Dk, Df, Tg, Coefficient of Thermal Expansion (CTE), thermal stability, Pb-free compatibility, vendor availability, and cost, in line with IPC-4101 material classes. Our portfolio covers stack-ups up to 28 layers with laser microvias, buried vias, back-drilling, and flex/rigid-flex - the construction style imposed by the densest FPGAs and by the coexistence of FPGA + DDR + PCIe + RF on a single board.

FPGA families we master:

• Xilinx (AMD): Spartan, Artix, Kintex, Virtex, Zynq (SoC FPGA), Versal (AI adaptive)
• Intel (Altera): Cyclone, Arria, Stratix, Agilex
• Lattice: iCE40, ECP5, CrossLink, Certus, for low-power applications

Associated competencies:

• VHDL and Verilog development
• High-density BGA routing (1000+ pin packages)
• High-speed interfaces: DDR3/DDR4/DDR5, PCIe Gen3/Gen4, multi-Gbps transceivers
• Thermal management for high-power FPGAs
• CE/EMC certification for FPGA systems

FPGA: accelerating innovation without sacrificing flexibility

For technical decision-makers, the FPGA is a uniquely strategic lever: it combines hardware-class processing power with software-style upgrade flexibility. At AESTECHNO, we have observed that FPGA projects scoped properly from day one significantly cut development time and the risk of expensive iterations.

Designing an FPGA board involves high-speed routing constraints (DDR, PCI Express, multi-Gbps transceivers) and rigorous thermal management. The choice between FPGA and embedded GPU (NVIDIA Jetson) depends on your latency, volume, and upgradability constraints. Our design office guarantees a smooth path from prototype to industrialisation.

Bottom line

The bottom line on FPGA board design pulls together the five non-negotiables we apply on every Xilinx, Intel, and Lattice project: device sizing with headroom, multi-rail power sequencing per the vendor PG, SerDes characterisation with Tektronix TekExpress and Keysight VNA, ANSYS SIwave PDN and SI sign-off, and an 8-layer minimum stack-up above 10 Gbps. Skip any of these and a re-spin becomes the default outcome.

• Pick the right family first: AMD/Xilinx Versal Premium and Intel/Altera Agilex for 56-112 Gbps PAM4, Lattice Avant or Microchip Microsemi PolarFire for low-power edge work, Artix and Kintex for cost-balanced DSP and vision pipelines.
• Plan SerDes characterisation up front: Tektronix TekExpress automated compliance plus Keysight VNA insertion-loss sweep is the bench duo we use on every FPGA board we deliver.
• Default to 8 layers above 10 Gbps: in our practice, the 4 dB insertion-loss drop at 5 GHz from explicit reference vias and back-drilling pays for itself by avoiding a second re-spin.
• Sign off PDN and SI in ANSYS SIwave: target-impedance and IR-drop on VCCINT, MGTAVCC, MGTAVTT, cross-checked against the AMD/Xilinx PG047 PDN guide and Cadence Allegro / Sigrity pre-layout sweeps.
• Test on real hardware, not just simulation: real-world measurement across a batch (we profiled 20 Versal Premium boards on a recent project) catches what the simulator misses, especially on the corner cases that drive field returns.

FAQ: FPGA board design

FPGA or MCU: how to choose?
The microcontroller fits sequential applications with low cost and low power constraints: IoT, motor control, user interfaces. The FPGA earns its place as soon as the project requires intensive parallel processing, deterministic latency on the order of nanoseconds, or custom high-speed interfaces. If your application combines both needs, FPGA SoCs (such as Xilinx Zynq) integrate an ARM processor and programmable logic on the same chip.

What does FPGA board development cost?
The NRE cost of an FPGA project is significantly higher than an MCU project, but markedly lower than an ASIC. The budget depends on board complexity (number of high-speed interfaces, FPGA density), the volume of logic to develop in VHDL/Verilog, and certification constraints. We size every project to what is actually needed to optimise the performance-to-investment ratio. Contact us for an estimate matched to your specification.

FPGA for pre-ASIC prototyping: is this a good strategy?
It is in fact a recommended strategy. The FPGA lets you validate the full hardware architecture under real conditions before committing to the very high NRE cost of an ASIC. You can test interfaces, refine algorithms, and verify performance in operational conditions. This approach significantly reduces error risk when moving to silicon. At AESTECHNO, we have supported several clients through this FPGA-to-ASIC transition.

Which FPGAs for embedded AI?
For AI inference acceleration, the most suitable families are Xilinx Versal (with integrated AI Engine blocks), Zynq UltraScale+ (combining FPGA and ARM processor), and Intel Agilex. The choice depends on your model size, target latency, and energy budget. The FPGA gives you a custom AI accelerator optimised for your specific model, where an embedded GPU offers more software flexibility.

Does AESTECHNO have high-performance FPGA experience?
High-performance FPGAs are one of our specialty domains. We have designed and delivered boards involving millions of logic gates, power budgets of several hundred watts, and serial links at tens of Gbps. We master high-density BGA routing, the associated thermal management, and full VHDL/Verilog development. Our combined analogue and digital competency lets us guarantee signal integrity on the most demanding interfaces.

Can FPGA logic be updated after deployment?
Yes - this is a major advantage of the FPGA over the ASIC. Bitstream updates are possible via external SPI flash, JTAG, or network interfaces (Ethernet, USB) for remote updates. SRAM-based FPGAs (the bulk of the market) require configuration reload at every power-up, while flash-based FPGAs retain their configuration. OTA updates allow bug fixes or feature additions with no hardware recall - a decisive asset for field deployments.

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