PCI Express pinout: the card-edge connector, x1 to x16

Side A, side B and pair direction

Side B is the component side of the card, side A the solder side. Pins A1 and B1 face each other, one on each side of the card. Pin 1 is at the bracket end: the short segment of pins 1 to 11 carries power and the sideband signals, and the distance from the key notch to the bracket is the same for every width.

The classic trap is the pair naming. The CEM names the pairs from the system board: PETp0/PETn0 (B14, B15) is the system board transmitter, which the card receives; PERp0/PERn0 (A16, A17) is the card transmitter. On an add-in card, the PCIe device’s transmit pair therefore goes to side A and its receive pair comes from side B. The public card tables from NVIDIA and LimeFEA confirm it: B14 is the card RX input there, A16 its TX output.

PRSNT1# and PRSNT2#: wiring per width

Each connector width ends with a PRSNT2# pin: B17 for x1, B31 for x4, B48 for x8, B81 for x16. On the card, PRSNT1# (A1) is tied by a trace to the farthest PRSNT2# pin, the one of its own width. The intermediate PRSNT2# pins stay unconnected: an x4 card ties A1 to B31 and leaves B17 open, an x16 card ties A1 to B81 and leaves B17, B31 and B48 open.

On the system board, this loop serves presence detection for hot-plug: the PRSNT2# that comes back tied to PRSNT1# tells that a card is in place and its mechanical width. The PRSNT contacts are shorter than the others, so they only connect once the card is fully inserted.

PERST#, REFCLK and CLKREQ#

PERST# (A11) is the fundamental reset, driven by the system board. The CEM requires it to stay asserted for at least 100 ms after the supplies are stable, and at least 100 µs after REFCLK is stable. It must be asserted again within 500 ns of a supply going out of tolerance, and a reset pulse lasts at least 100 µs.

REFCLK+/REFCLK- (A13, A14) is the reference clock supplied by the system board: 100 MHz in HCSL logic, ±300 ppm up to PCIe 4.0 and ±100 ppm for PCIe 5.0 and 6.0. Spread spectrum clocking (SSC) is not required by the specification; it cuts emissions, and congatec enables it by default on most of its x86 products.

CLKREQ# (B12) came with the 2013 L1 PM Substates ECN; the pin was reserved before. It is an optional open-drain signal that the card pulls low to request the reference clock; with L1 substates, either the system board or the card can assert it to exit L1. The pull-up is on the system board.

WAKE#, +3.3Vaux, SMBus, JTAG and PWRBRK#

WAKE# (B11) is an open-drain, active-low signal, with the pull-up on the system board. It is only required if the card or the system supports wakeup (or the OBFF mechanism). To wake a powered-down machine, the card needs standby power: that is the job of +3.3Vaux (B10), optional on the system side, limited to 375 mA by the CEM.

SMBus (SMCLK B5, SMDAT B6) and JTAG (A5 to A8, TRST# on B9) are optional, each as a block: if the function is implemented, all its pins are. SMBus input levels are referenced to the 3.3 V standby supply, not the main +3.3 V. The NVIDIA BlueField and LimeFEA cards listed in the sources leave JTAG unconnected.

PWRBRK# (B30, from x4 up) was defined by a 2015 ECN on a pin that was reserved until then. Open drain, active low, driven by the system: a card that supports it must cut its power within 10 µs. The card carries a weak pull-up (95 kΩ minimum), the system a stronger one. The ECN mentions earlier proprietary uses of B30: a system board that pulls it low can throttle a recent card.

AC coupling caps, polarity and lane reversal

Every pair is AC coupled, and the capacitors go on the transmitter side: the add-in card carries those of its PERp/PERn pairs (side A), the system board those of its PETp/PETn pairs (side B). A card therefore puts no capacitor on the pairs it receives. The base specification asks for 75 to 265 nF at Gen 1 and 2, 176 to 265 nF at Gen 3: a 220 nF value covers both.

Polarity inversion is mandatory for every PCI Express receiver, on each lane independently: you may swap p and n of a data pair to simplify routing, and the receiver corrects it during link training. The Raspberry Pi CM4 IO board does this on its x1 slot. Lane reversal (lane 0 on lane 3) is optional, however: check that one of the two devices supports it before routing an x4 link reversed.

Power available from the slot

All the supplies sit on pins 1 to 11: a wider connector adds no power pin. Whatever the width, +3.3 V is limited to 3 A. What changes is +12 V and the total power: an x1 card is limited to 10 W (0.5 A on +12 V); an x4 or wider card to 25 W (2.1 A on +12 V). A full-height x1 card may go up to 25 W once software configures it as a high-power device.

A full-size x16 graphics card may draw 75 W from the slot (5.5 A on +12 V) after high-power configuration. Beyond that, power comes through the 6 or 8-pin auxiliary connectors, not the card edge. +3.3Vaux is limited to 375 mA. Size the card to the budget of its own width, not to that of the slot it sits in.

x8 and x16: the same pattern, continued

From pin 33 on, each lane takes four pins and the pattern repeats. On side B, the lane 4 PET pair is on B33-B34, lane 5 on B37-B38, and so on every four pins; on side A, the PER pair is offset by two pins (lane 4 on A35-A36, lane 7 on A47-A48). The remaining pins are grounds. The x8 connector ends at pin 49, with PRSNT2# on B48; A32 and A33 are reserved.

x16 resumes at pin 50 with a one-pin offset: A50 is reserved, lane 8 transmits on B50-B51 and receives on A52-A53, up to lane 15 on B78-B79 and A80-A81. The connector ends at pin 82, with PRSNT2# on B81, B82 reserved and A82 grounded. An x16 card thus has all four possible PRSNT2# positions; it ties only one, B81.

A card fits a slot of its own size or larger, and the link negotiates the common width. The mechanical width does not guarantee the wired lanes: an x16 slot may be wired x4 only (written "x16 @ x4" or "x16 (x4 mode)").