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AESTECHNO
HJ / Cohn

Differential-pair impedance calculator

This calculator returns the differential impedance Zdiff of an edge-coupled pair, in microstrip or stripline. It first computes single-ended Z0 from real geometry (trace width, spacing, copper thickness, dielectric height, er), then applies the coupling correction. Target 90, 100 or 85 ohms.

Inputs

Topology

Topology

Microstrip: surface pair over one plane. Stripline: pair buried between two planes.

Length unit

w, s, t, h and b are entered in this unit (the math normalises to mm).

Dielectric

Relative permittivity of the substrate. FR4 is about 4.2 to 4.6.

Geometry

Width of one of the two traces in the pair.

Bare copper gap between the two traces. Smaller s means stronger coupling and lower Zdiff.

0.035 mm equals 1 oz, 0.0175 mm equals 0.5 oz.

Dielectric thickness between the trace and the reference plane.

Total distance between the two reference planes, with the pair centred.

Crosstalk

Crosstalk

Near-end (NEXT) and far-end (FEXT) crosstalk between the two traces, from the even/odd modes.

Length over which the two traces run in parallel (in inches).

Aggressor 10-90% rise time. Shorter rise time means stronger FEXT.

Step amplitude on the aggressor trace (victim assumed terminated).

Ground plane Dielectric · εr Differential pair W S T H

Cross-section (not to scale)

Result

123.6 Ω

Breakdown

target 100 Ω (Ethernet / LVDS / PCIe)

Even-mode Z0e 82.53 Ω
Odd-mode Z0o 61.8 Ω
Common-mode Z 41.26 Ω
Single-ended Z0 71.42 Ω
εeff (even / odd) 3.24 / 2.78
Propagation delay 5.557 ps/mm · 141.1 ps/in
Coupling 16.9 dB

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You receive the result with its direct link. Our design house gets a copy and can react to it, simply reply if you want an engineer's eye on it.

Hammerstad-Jensen coupled-microstrip / Cohn coupled-stripline even-odd model, ~1-2% of a 2D field solver. Copper thickness is not yet modelled in the pair; confirm tight geometries against the fab stack-up or a field solver.

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A differential pair that misses its 90, 100 or 85 ohm target can sink a high-speed link. Let us help: book a free 30-minute audit with our design house.

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Frequently asked questions

FAQ

How does the calculator get Zdiff from the geometry?
With a true even/odd-mode coupled-line model. For microstrip we use the Hammerstad-Jensen coupled model, for stripline the Cohn model (elliptic integrals), from the geometry w, s, h (or b) and er. The calculator returns the even-mode Z0e and odd-mode Z0o impedances, then Zdiff = 2 x Z0o and Zcommon = Z0e / 2. You never have to supply Z0 yourself.
Why does spacing s lower Zdiff so much?
Edge-to-edge spacing s is the coupling lever. Smaller s means the two traces couple more strongly and Zdiff drops. As s grows, the term exp(-a x s / h) approaches zero, coupling vanishes and Zdiff approaches 2 x Z0 (two independent traces). That is why tightening the pair is the first move when your Zdiff is too high, and widening it when Zdiff is too low.
How accurate is this calculation?
The Hammerstad-Jensen and Cohn even/odd-mode models are accurate to roughly 1 to 2 percent of a 2D field solver, far better than the old exponential corrections. Copper thickness is not yet modelled in the pair, and the closed forms do not cover trapezoidal etch, roughness or dispersion. For any critical pair (USB 3, PCIe, MIPI, Ethernet), confirm against your fabricator's stackup or a 2D field solver before freezing the geometry.
What are the 90, 100 and 85 ohm targets for?
90 ohm differential: USB 2.0 and USB 3.x SuperSpeed lanes. 100 ohm differential: Ethernet, LVDS, PCI Express and most generic pairs. 85 ohm differential: SATA and some PCIe pairs depending on fabricator rules. Adjust w and s until Zdiff lands on the target, then lock the geometry into your routing constraints.
Microstrip or stripline: which topology should I pick?
Edge-coupled microstrip puts the pair on the surface over a single plane: simpler, lower loss, but more exposed to noise and etch variation. Stripline buries the pair between two planes: better shielding and reduced crosstalk, ideal at high speed, at the cost of extra vias and higher dielectric loss. The calculator handles both via the topology selector.
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AESTECHNO is an electronics design house based in Montpellier, France. Over 10 years of high-speed PCB design experience, with a 100 percent first-pass record on CE and FCC certification.