SD and microSD card pinout: SD bus and SPI modes

SD bus mode or SPI mode?

The card starts in SD bus mode. It switches to SPI mode if CS is held low during the first CMD0 command, and only a power cycle brings it back to SD mode. SPI runs from any microcontroller SPI peripheral, at a cost in performance: one data line and one hardware CS per card.

What SPI does not do, per chapter 7 of the specification: no UHS-I, no guaranteed speed class (the host treats the card as class 0), no boot, no RPMB access, and functions added after version 2.00 must not be used. SDUC cards (above 2 TB) do not support SPI mode at all.

In SPI, command CRC is off by default, except for CMD0, which the card receives while still in SD mode: its CRC must be valid.

Pull-up resistors on CMD and DAT

CMD and DAT0 to DAT3 are pulled up to VDD on the host side, including the lines left unused in 1-bit or SPI mode. Espressif asks for 10 kOhm on those five lines; Kingston gives 10 to 100 kOhm for the pins reserved in SPI. A floating DAT1 or DAT2 can put the card in the wrong state.

The specification states that DAT1 to DAT3 are inputs at power-up and only become data lines after the SET_BUS_WIDTH command. While it does not use them, the host keeps its own DAT1 to DAT3 as inputs too.

Detecting the card: CD/DAT3 or the socket switch

At power-up, the card enables a 50 kOhm internal pull-up on CD/DAT3. The host detects the card by seeing the line go high, and the same pull-up selects the mode: left high, the line keeps SD mode; driven low, it selects SPI. The ACMD42 command disconnects this pull-up during transfers.

This method does not work with an external pull-up on DAT3: the line is then high with or without a card. That is why we most often use the socket’s card-detect switch. The Multicomp Pro MP013694 microSD socket, for example, adds two pins, CD1 and CD2, to its 8 contacts. If the product must honor an SD card’s write-protect slider, only a socket switch can read it: the card has no WP pin.

3.3 V or 1.8 V: UHS-I signaling

The card is always powered from 2.7 to 3.6 V and starts with 3.3 V signaling: Default Speed up to 25 MHz, High Speed up to 50 MHz. The UHS-I modes SDR50, DDR50 and SDR104 (up to 208 MHz) move CLK, CMD and DAT0 to DAT3 to 1.8 V, the card deriving that level from its 3.3 V supply.

The switch to 1.8 V is negotiated: the host requests it in ACMD41, the card accepts, then CMD11 starts the switch sequence. A 3.3 V-only host therefore works with a UHS-I card, without the fast modes. In hardware, the host I/O must be able to move from 3.3 V to 1.8 V (dual-voltage I/O or a level translator). Once at 1.8 V, the card returns to neither 3.3 V nor SPI without a power cycle: plan a switch on VDD.

Card power-up

Figure 6-5 of the specification sets the host-side sequence: VDD held below 0.5 V for at least 1 ms, then a ramp as monotonic as possible, from 0.1 ms to 35 ms. VDD must reach its minimum within 250 ms. The host then sends at least 74 clock cycles with CMD high (CS high in SPI) before the first command.

The 1 ms minimum below 0.5 V matters for restarts: a decoupling capacitor that drains slowly through a light load can leave VDD too high and the card in an undefined state. A load switch with active discharge solves it.

ESD protection at the socket

The contacts of a removable card are touched at every insertion. The full specification has a section on ESD requirements, left blank in the simplified version; on the host board, we place a protection diode array as close to the socket as possible, on CLK, CMD and DAT0 to DAT3.

The choice depends on the target speed. An integrated EMI and ESD filter such as the TI TPD6F003 (100 Ohm and 17 pF RC filter, 200 MHz at -3 dB, IEC 61000-4-2 level 4) suits memory cards at modest speeds. For SDR104 at 208 MHz, we prefer very low capacitance diodes, with no series resistor.

Dimensions: SD and microSD to scale

The SD card measures 24 × 32 mm, 2.1 mm thick (1.4 mm for the thin version). The microSD measures 11 × 15 mm, 1.0 mm thick. Both have their contacts along the insertion edge, on the face opposite the label.

UHS-II, SD Express and the second row

A UHS-II card keeps the first row to stay compatible with standard SD hosts and adds a second row: two differential lanes, D0 and D1, a second 1.8 V supply, VDD2, and three grounds. In UHS-II mode, the card no longer drives CLK, CMD, DAT3 or DAT2; the host must hold them at a defined level, with CLK low.

The UHS-II microSD also has a second row (Figure L-6 of the specification), but its assignment is in the microSD addendum, which is not public: we do not publish it. SD Express cards use the second row for a PCIe link with the NVMe protocol.