Which VGA pins carry DDC and the EDID?

Pin 12 carries the data (SDA) and pin 15 the clock (SCL) of an I²C bus, referenced to the +5 V the host supplies on pin 9. The display’s EDID is read at address A0h/A1h. Before DDC, these two pins carried monitor ID bits 1 and 3: never tie them to ground in a DDC design.

Is VGA pin 9 a key or +5 V?

Both, depending on the era. On the original VGA, position 9 was not connected and served as the key. Since DDC it is the host’s +5 V: 5 V ± 5 %, 50 mA, limited to 1 A at most per VESA E-DDC. The contact is recessed 1.27 mm in the socket so it mates last. Some monitor manuals label it “5 V/3.3 V”.

What level and impedance for the red, green and blue signals?

Dell monitor specifications give 0.7 V ± 5 %, positive polarity, at 75 Ω input impedance. Each colour has its own return: red on 6, green on 7, blue on 8. The reference electrical standard, VESA VSIS, is not public; in a design, treat each colour as a 75 Ω line terminated at the display.

What is the difference between DVI-D and DVI-I?

DVI-D (the digital-only connector) has 24 contacts in three rows of eight. DVI-I (the combined connector) adds five analog contacts, C1 to C5: red, green, blue, horizontal sync and analog ground, and uses pin 8 for vertical sync. An analog plug will not go into a DVI-D socket, which lacks the C1 to C4 contacts.

When is dual-link DVI needed?

Whenever the pixel format and its blanking need more than a 165 MHz TMDS clock, the single-link limit in the DVI 1.0 specification. The second link uses pairs 3, 4 and 5 on pins 4, 5, 12, 13, 20 and 21, and each link then runs at half the frequency. A single-link monitor such as the Dell U2412M leaves those six pins floating.

Pinout

VGA pinout (DE-15) and DVI pinout

The VGA connector is a 15-pin high-density D-sub in three rows, called DE-15 or HD15. It carries analog red, green and blue video with their returns, horizontal and vertical sync, and the DDC bus that reads the display’s EDID, powered from the +5 V on pin 9.

By Hugues Orgitello · Updated November 4, 2026 ·

VGA DE-15 (HD15), 15 pins

Signal names from the VESA E-DDC 1.2 standard (Table 7-1, “DDC / E-DDC Host” column); the right-hand column gives the original VGA role. Direction is seen from the host (graphics card). Female socket: pin 1 top right; on the cable’s male plug it moves to the top left.

Pin	Signal	Dir.	Legacy VGA (before DDC)	Description
1	Red video	Out	Red video	Red video, analog (Signal)
2	Green video	Out	Green video	Green video, analog; may carry sync on green (SOG) when both the display and the host support it (Signal)
3	Blue video	Out	Blue video	Blue video, analog (Signal)
4	ID2 / Reserved		Monitor ID bit 2	Monitor ID bit 2 on the host side; reserved, not connected on a DDC display (Configuration)
5	Return (ground)		Test (ground)	Return (ground) (Ground)
6	Red return		Red return	Red video return (Ground)
7	Green return		Green return	Green video return (Ground)
8	Blue return		Blue return	Blue video return (Ground)
9	+5V (DDC)	Out	No connection (mechanical key)	+5 V ± 5 % from the host for the EDID, 50 mA, current-limited to 1 A at most; contact recessed 1.27 mm in the socket (Power)
10	Sync return		Sync return	Synchronization return (Ground)
11	ID0 / Reserved		Monitor ID bit 0	Monitor ID bit 0 on the host side; reserved, not connected on a DDC display (Configuration)
12	SDA	I/O	Monitor ID bit 1	DDC data (I²C): reads the EDID (Signal)
13	HSync	Out	Horizontal sync	Horizontal sync; may carry composite sync when both the display and the host support it (Signal)
14	VSync	Out	Vertical sync	Vertical sync (Signal)
15	SCL	Out	Monitor ID bit 3	DDC clock (I²C) (Signal)

DVI-I (24 + 5 pins) and DVI-D (24 pins)

DDWG DVI 1.0 specification, Table 5-2 (combined connector, DVI-I); the DVI-D column follows Table 5-1 (digital-only connector). Direction is seen from the host. Link 1 pins are only used in dual link, above a 165 MHz TMDS clock.

Pin	Signal	Dir.	TMDS link	On DVI-D	Description
1	TMDS Data2-	Out	Link 0	Same	TMDS data pair 2, negative (Differential pair)
2	TMDS Data2+	Out	Link 0	Same	TMDS data pair 2, positive (Differential pair)
3	TMDS Data2/4 Shield		Links 0 and 1	Same	Shield shared by pairs 2 (link 0) and 4 (link 1), tied to ground (Shield / earth)
4	TMDS Data4-	Out	Link 1 (dual link)	Same	TMDS data pair 4, negative (Differential pair)
5	TMDS Data4+	Out	Link 1 (dual link)	Same	TMDS data pair 4, positive (Differential pair)
6	DDC Clock	Out	Not TMDS	Same	DDC clock (I²C) (Signal)
7	DDC Data	I/O	Not TMDS	Same	DDC data (I²C): reads the EDID (Signal)
8	Analog Vertical Sync	Out	Not TMDS	No Connect	Analog vertical sync (Signal)
9	TMDS Data1-	Out	Link 0	Same	TMDS data pair 1, negative (Differential pair)
10	TMDS Data1+	Out	Link 0	Same	TMDS data pair 1, positive (Differential pair)
11	TMDS Data1/3 Shield		Links 0 and 1	Same	Shield shared by pairs 1 (link 0) and 3 (link 1), tied to ground (Shield / earth)
12	TMDS Data3-	Out	Link 1 (dual link)	Same	TMDS data pair 3, negative (Differential pair)
13	TMDS Data3+	Out	Link 1 (dual link)	Same	TMDS data pair 3, positive (Differential pair)
14	+5V Power	Out	Not TMDS	Same	+5 V from the host for the EDID: 55 mA minimum (Power)
15	Ground		Not TMDS	Ground (for +5V)	Ground: return for +5 V, HSync and VSync (Ground)
16	Hot Plug Detect	In	Not TMDS	Same	Hot plug detect: the monitor drives it above 2.4 V once its EDID can be read (Signal)
17	TMDS Data0-	Out	Link 0	Same	TMDS data pair 0, negative (Differential pair)
18	TMDS Data0+	Out	Link 0	Same	TMDS data pair 0, positive (Differential pair)
19	TMDS Data0/5 Shield		Links 0 and 1	Same	Shield shared by pairs 0 (link 0) and 5 (link 1), tied to ground (Shield / earth)
20	TMDS Data5-	Out	Link 1 (dual link)	Same	TMDS data pair 5, negative (Differential pair)
21	TMDS Data5+	Out	Link 1 (dual link)	Same	TMDS data pair 5, positive (Differential pair)
22	TMDS Clock Shield		Links 0 and 1	Same	Clock pair shield, tied to ground (Shield / earth)
23	TMDS Clock+	Out	Links 0 and 1	Same	TMDS clock pair, positive, shared by both links (Differential pair)
24	TMDS Clock-	Out	Links 0 and 1	Same	TMDS clock pair, negative (Differential pair)
C1	Analog Red	Out	Not TMDS	Not present	Analog red video (Signal)
C2	Analog Green	Out	Not TMDS	Not present	Analog green video (Signal)
C3	Analog Blue	Out	Not TMDS	Not present	Analog blue video (Signal)
C4	Analog Horizontal Sync	Out	Not TMDS	Not present	Analog horizontal sync (Signal)
C5	Analog Ground		Not TMDS	Not present	Analog ground: return for red, green and blue only (Ground)

An interface to design?

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Reading the face: socket, plug and pin 9

The drawing shows the graphics card’s female socket seen from the front, wide side of the trapezoid up: top row 5 to 1 from left to right, middle row 10 to 6 offset half a pitch to the right, bottom row 15 to 11. The cable’s male plug reads mirrored: pin 1 moves to the top left. That is the view of E-DDC Figure 7-1 and of the Kycon K61X drawing.

The E-DDC standard sets two mechanical differences from the original VGA: socket contact 9 is recessed by 0.050 inch (1.27 mm), which per Kycon makes +5 V mate last and break first, and the host-side socket insulator is royal blue to mark a DDC port. On the oldest cables pin 9 is missing: it was the mechanical key.

Analog signal levels

Dell monitor specifications (P2419H, U2412M) give the RGB input as 0.7 V ± 5 %, positive polarity, at 75 Ω input impedance, and the U2412M sheet adds separate syncs at TTL levels, with sync on green as an option. Each colour lands on 75 Ω: route the red, green and blue traces as 75 Ω lines and bring each return (6, 7, 8) back close by.

The electrical standard for the analog signal is the VESA Video Signal Standard (VSIS), which the DVI 1.0 specification makes mandatory for the analog part of DVI-I. That document is not public: the values above come from monitor specifications, not from VSIS.

DDC, EDID and +5 V: what the E-DDC standard says

DDC bus. SDA on pin 12, SCL on pin 15: it is an I²C bus. The host pulls them up to +5 V through 1.5 to 2.2 kΩ, or with a 3 mA current source; the display only adds 47 kΩ on SCL. The EDID is read at address A0h/A1h, and E-DDC adds a segment pointer at 60h for EDID beyond 256 bytes.

+5 V on pin 9. Every host, battery-powered ones included, supplies +5 V ± 5 % whenever its video port is active, with 50 mA capability and protection that limits the current to 1 A at most. With the display off it may draw 50 mA from it; switched on, 1 mA at most. The EDID must be readable 20 ms after +5 V appears, even with the display off.

DDC1, dropped. The original DDC had a one-way mode, display to host, called DDC1. E-DDC 1.2 removed it: VESA no longer supports it and advises against it for any new design, which should follow E-DDC over I²C.

Pins 4, 5, 11, 12 and 15: the old monitor ID bits

Before DDC, the display identified itself by tying some pins to ground: ID bits 0 to 3 on pins 11, 12, 4 and 15, and pin 5 marked “test”. DDC took pin 12 for SDA and pin 15 for SCL; the E-DDC standard keeps ID0 and ID2 on the host side and declares them reserved, not connected, on the display side.

Commercial displays do not all follow that rule: the Dell P2419H and U2412M manuals call pins 4 and 11 GND and pin 5 “Self-test”. A board driving a display should assume nothing about pins 4 and 11, and a board receiving VGA should put no signal on them.

DVI: single link, dual link, DVI-I and DVI-D

Single and dual link. Link 0 (pairs 0, 1, 2 and the clock) carries every format up to a 165 MHz TMDS clock. Above that, the second link (pairs 3, 4, 5, pins 4, 5, 12, 13, 20 and 21) becomes mandatory and each link runs at half the frequency. Both links share the clock pair and three common shields.

DVI-I and DVI-D. The digital-only connector has no C1 to C4 contacts: an analog monitor’s plug will not go in. On DVI-I, the VGA functions sit as follows: red, green, blue on C1 to C3 with their return on C5, horizontal sync on C4, vertical sync on pin 8, DDC on 6 and 7, +5 V on 14, and the sync and +5 V ground on 15.

HPD and +5 V. The monitor raises HPD above 2.4 V only once its EDID can be read, and holds it below 0.4 V otherwise; the host reacts to crossings above 2.0 V or below 0.8 V. The +5 V supplies at least 55 mA; the monitor draws no more than 50 mA when off and 10 mA when on. On insertion the shell mates first, then C5, then the pins, and last C1 to C4 and pin 14.

Frequently asked questions

FAQ

Which VGA pins carry DDC and the EDID?: Pin 12 carries the data (SDA) and pin 15 the clock (SCL) of an I²C bus, referenced to the +5 V the host supplies on pin 9. The display’s EDID is read at address A0h/A1h. Before DDC, these two pins carried monitor ID bits 1 and 3: never tie them to ground in a DDC design.
Is VGA pin 9 a key or +5 V?: Both, depending on the era. On the original VGA, position 9 was not connected and served as the key. Since DDC it is the host’s +5 V: 5 V ± 5 %, 50 mA, limited to 1 A at most per VESA E-DDC. The contact is recessed 1.27 mm in the socket so it mates last. Some monitor manuals label it “5 V/3.3 V”.
What level and impedance for the red, green and blue signals?: Dell monitor specifications give 0.7 V ± 5 %, positive polarity, at 75 Ω input impedance. Each colour has its own return: red on 6, green on 7, blue on 8. The reference electrical standard, VESA VSIS, is not public; in a design, treat each colour as a 75 Ω line terminated at the display.
What is the difference between DVI-D and DVI-I?: DVI-D (the digital-only connector) has 24 contacts in three rows of eight. DVI-I (the combined connector) adds five analog contacts, C1 to C5: red, green, blue, horizontal sync and analog ground, and uses pin 8 for vertical sync. An analog plug will not go into a DVI-D socket, which lacks the C1 to C4 contacts.
When is dual-link DVI needed?: Whenever the pixel format and its blanking need more than a 165 MHz TMDS clock, the single-link limit in the DVI 1.0 specification. The second link uses pairs 3, 4 and 5 on pins 4, 5, 12, 13, 20 and 21, and each link then runs at half the frequency. A single-link monitor such as the Dell U2412M leaves those six pins floating.

Sources

Tables built from these documents and cross-checked against manufacturer datasheets. Always check the datasheet of the connector you actually use: some manufacturers number differently.