Skip to content
AESTECHNO
Pinout

M.2 pinout: Key M, Key B and Key E sockets

The M.2 connector (called NGFF, Next Generation Form Factor, before it was standardized) has 75 positions at 0.5 mm pitch: odd pins on the top side of the card, even pins underneath. The key removes eight positions: 59 to 66 for Key M (PCIe x4 or SATA SSDs), 12 to 19 for Key B (4G/5G modems, PCIe x2, USB 3) and 24 to 31 for Key E (Wi-Fi, Bluetooth).

By Hugues Orgitello · Updated ·

Socket 3, Key M: PCIe x4 or SATA SSD

Positions 59 to 66 are removed by the key. In SATA mode, pair A (host transmit) sits on 47/49 and pair B (host receive) on 41/43. Direction seen from the host, the board that carries the socket. Signal names as congatec AN43 reproduces them from the M.2 specification: PER is received by the host, so the card transmits on it.

M.2 (keys M, B and E) · Socket 3, Key M: PCIe x4 or SATA SSD. M.2 card edge seen from its top (component) side, contacts pointing down, pin 1 on the right. Top row: odd contacts, top side. Bottom row: even contacts, underside, drawn as if seen through the card..
M.2 card edge seen from its top (component) side, contacts pointing down, pin 1 on the right. Top row: odd contacts, top side. Bottom row: even contacts, underside, drawn as if seen through the card.
Pin Signal Dir. Level Description
1 GND - Ground (Ground)
2 3.3V 3.3 V 3.3 V card supply (Power)
3 GND - Ground (Ground)
4 3.3V 3.3 V 3.3 V card supply (Power)
5 PERn3 In - PCIe lane 3, transmitted by the card, negative (Differential pair)
6 NC - Not connected (Not connected)
7 PERp3 In - PCIe lane 3, transmitted by the card, positive (Differential pair)
8 NC - Not connected (Not connected)
9 GND - Ground (Ground)
10 DAS/DSS / LED_1# I/O 3.3 V SSD activity for an LED, active low; in SATA, DAS/DSS (activity, or disable staggered spin-up) (Signal)
11 PETn3 Out - PCIe lane 3, transmitted by the host, negative (Differential pair)
12 3.3V 3.3 V 3.3 V card supply (Power)
13 PETp3 Out - PCIe lane 3, transmitted by the host, positive (Differential pair)
14 3.3V 3.3 V 3.3 V card supply (Power)
15 GND - Ground (Ground)
16 3.3V 3.3 V 3.3 V card supply (Power)
17 PERn2 In - PCIe lane 2, transmitted by the card, negative (Differential pair)
18 3.3V 3.3 V 3.3 V card supply (Power)
19 PERp2 In - PCIe lane 2, transmitted by the card, positive (Differential pair)
20 NC - Not connected (Not connected)
21 GND - Ground (Ground)
22 NC - Not connected (Not connected)
23 PETn2 Out - PCIe lane 2, transmitted by the host, negative (Differential pair)
24 NC - Not connected (Not connected)
25 PETp2 Out - PCIe lane 2, transmitted by the host, positive (Differential pair)
26 NC - Not connected (Not connected)
27 GND - Ground (Ground)
28 NC - Not connected (Not connected)
29 PERn1 In - PCIe lane 1, transmitted by the card, negative (Differential pair)
30 NC - Not connected (Not connected)
31 PERp1 In - PCIe lane 1, transmitted by the card, positive (Differential pair)
32 NC - Not connected (Not connected)
33 GND - Ground (Ground)
34 NC - Not connected (Not connected)
35 PETn1 Out - PCIe lane 1, transmitted by the host, negative (Differential pair)
36 NC - Not connected (Not connected)
37 PETp1 Out - PCIe lane 1, transmitted by the host, positive (Differential pair)
38 DEVSLP Out - SATA Device Sleep: when high, the host asks the SSD to enter a low-power state (optional) (Signal)
39 GND - Ground (Ground)
40 SMB_CLK I/O 1.8 V SMBus clock, open drain, pulled up on the host (Signal)
41 PERn0 / SATA-B+ In - PCIe lane 0 transmitted by the card, negative; in SATA, pair B positive (host receive) (Differential pair)
42 SMB_DATA I/O 1.8 V SMBus data, open drain, pulled up on the host (Signal)
43 PERp0 / SATA-B- In - PCIe lane 0 transmitted by the card, positive; in SATA, pair B negative (Differential pair)
44 ALERT# In 1.8 V SMBus alert from the card to the host, active low (Signal)
45 GND - Ground (Ground)
46 NC - Not connected (Not connected)
47 PETn0 / SATA-A- Out - PCIe lane 0 transmitted by the host, negative; in SATA, pair A negative (host transmit) (Differential pair)
48 NC - Not connected (Not connected)
49 PETp0 / SATA-A+ Out - PCIe lane 0 transmitted by the host, positive; in SATA, pair A positive (Differential pair)
50 PERST# Out 3.3 V PCIe functional reset of the card, active low (Signal)
51 GND - Ground (Ground)
52 CLKREQ# I/O 3.3 V Reference clock request, open drain, also used by L1 PM substates (Signal)
53 REFCLKn Out - PCIe 100 MHz reference clock, negative (Differential pair)
54 PEWAKE# I/O 3.3 V PCIe wake request from the card, open drain, active low (Signal)
55 REFCLKp Out - PCIe 100 MHz reference clock, positive (Differential pair)
56 NC (MFG_DATA) - Reserved for SSD manufacturing, leave unconnected on the host (Not connected)
57 GND - Ground (Ground)
58 NC (MFG_CLOCK) - Reserved for SSD manufacturing, leave unconnected on the host (Not connected)
67 NC - Not connected (Not connected)
68 SUSCLK Out 3.3 V 32.768 kHz suspend clock supplied by the host (Signal)
69 PEDET In - Protocol detect: grounded on a SATA card, unconnected on a PCIe card; pulled up on the host (Configuration)
70 3.3V 3.3 V 3.3 V card supply (Power)
71 GND - Ground (Ground)
72 3.3V 3.3 V 3.3 V card supply (Power)
73 GND - Ground (Ground)
74 3.3V 3.3 V 3.3 V card supply (Power)
75 GND - Ground (Ground)

Socket 2, Key B: WWAN modem or SSD, PCIe x2, USB 3, SATA

Positions 12 to 19 are removed by the key. The GPIOs change role with the configuration read on CONFIG_0 to CONFIG_3; the description gives the use found on the Quectel RM520N-GL and SIMCom SIM8200EA-M2 5G modules. Direction seen from the host, the board that carries the socket. Signal names as congatec AN43 reproduces them from the M.2 specification: PER is received by the host, so the card transmits on it.

M.2 (keys M, B and E) · Socket 2, Key B: WWAN modem or SSD, PCIe x2, USB 3, SATA. M.2 card edge seen from its top (component) side, contacts pointing down, pin 1 on the right. Top row: odd contacts, top side. Bottom row: even contacts, underside, drawn as if seen through the card..
M.2 card edge seen from its top (component) side, contacts pointing down, pin 1 on the right. Top row: odd contacts, top side. Bottom row: even contacts, underside, drawn as if seen through the card.
Pin Signal Dir. Level Description
1 CONFIG_3 In - Card configuration, bit 3: grounded or unconnected on the card, pulled up on the host (Configuration)
2 3.3V 3.3 V 3.3 V card supply (Power)
3 GND - Ground (Ground)
4 3.3V 3.3 V 3.3 V card supply (Power)
5 GND - Ground (Ground)
6 FULL_CARD_POWER_OFF# Out 1.8 or 3.3 V Card power on: high = on. Pulled down inside the Quectel and SIMCom modules (Signal)
7 USB_D+ I/O - USB 2.0, positive (Differential pair)
8 W_DISABLE1# Out 3.3 V Radio off (airplane mode), active low (Signal)
9 USB_D- I/O - USB 2.0, negative (Differential pair)
10 GPIO_9 / DAS/DSS / LED_1# I/O 3.3 V Status LED, open drain, active low (WWAN modules); DAS/DSS on an SSD (Signal)
11 GND - Ground (Ground)
20 GPIO_5 I/O 1.8 V GPIO per configuration; I2S clock on the SIMCom, reserved on the Quectel (Signal)
21 CONFIG_0 In - Card configuration, bit 0 (Configuration)
22 GPIO_6 I/O 1.8 V GPIO per configuration; I2S data input on the SIMCom (Signal)
23 GPIO_11 I/O 1.8 V On both modules: WoWWAN#, modem wakes the host, open drain (Signal)
24 GPIO_7 I/O 1.8 V I2S data output on the SIMCom; 1.8 V supply output (50 mA) on the Quectel (Signal)
25 DPR Out 1.8 V Dynamic Power Reduction: when low, the modem lowers its maximum transmit power (Signal)
26 GPIO_10 / W_DISABLE2# I/O 1.8 V W_DISABLE2# on both modules: GNSS off, active low (Signal)
27 GND - Ground (Ground)
28 GPIO_8 I/O 1.8 V GPIO per configuration; I2S word select on the SIMCom (Signal)
29 PERn1 / USB3.1-Rx- / SSIC-RxN In - PCIe lane 1 or USB 3 SuperSpeed, transmitted by the card, negative (Differential pair)
30 UIM-RESET In - SIM card reset, driven by the module to the host SIM holder (Signal)
31 PERp1 / USB3.1-Rx+ / SSIC-RxP In - PCIe lane 1 or USB 3 SuperSpeed, transmitted by the card, positive (Differential pair)
32 UIM-CLK In - SIM card clock, driven by the module (Signal)
33 GND - Ground (Ground)
34 UIM-DATA I/O - SIM card data (Signal)
35 PETn1 / USB3.1-Tx- / SSIC-TxN Out - PCIe lane 1 or USB 3 SuperSpeed, transmitted by the host, negative (Differential pair)
36 UIM-PWR In 1.8 or 3 V SIM card supply, provided by the module (Power)
37 PETp1 / USB3.1-Tx+ / SSIC-TxP Out - PCIe lane 1 or USB 3 SuperSpeed, transmitted by the host, positive (Differential pair)
38 DEVSLP Out - SATA SSD Device Sleep; vendor-specific on WWAN modules (WLAN_TX_EN on Quectel, I2C_SCL on SIMCom) (Signal)
39 GND - Ground (Ground)
40 GPIO_0 / SMB_CLK I/O 1.8 V SMBus clock on an SSD; second SIM detect on both WWAN modules (Signal)
41 PERn0 / SATA-B+ In - PCIe lane 0 transmitted by the card, negative; in SATA, pair B positive (Differential pair)
42 GPIO_1 / SMB_DATA I/O 1.8 V SMBus data on an SSD; second SIM data on the WWAN modules (Signal)
43 PERp0 / SATA-B- In - PCIe lane 0 transmitted by the card, positive; in SATA, pair B negative (Differential pair)
44 GPIO_2 / ALERT# I/O 1.8 V SMBus alert on an SSD; second SIM clock on the WWAN modules (Signal)
45 GND - Ground (Ground)
46 GPIO_3 I/O 1.8 V Second SIM reset on the WWAN modules (Signal)
47 PETn0 / SATA-A- Out - PCIe lane 0 transmitted by the host, negative; in SATA, pair A negative (Differential pair)
48 GPIO_4 I/O 1.8 V Second SIM supply on the WWAN modules (Signal)
49 PETp0 / SATA-A+ Out - PCIe lane 0 transmitted by the host, positive; in SATA, pair A positive (Differential pair)
50 PERST# Out 3.3 V PCIe functional reset of the card, active low (Signal)
51 GND - Ground (Ground)
52 CLKREQ# I/O 3.3 V Reference clock request, open drain, pulled up on the host (Signal)
53 REFCLKn Out - PCIe reference clock, negative (Differential pair)
54 PEWAKE# I/O 3.3 V PCIe wake request from the card, open drain, pulled up on the host (Signal)
55 REFCLKp Out - PCIe reference clock, positive (Differential pair)
56 NC - Not connected per congatec; MIPI RFFE clock (antenna tuning) on both 5G modules (Not connected)
57 GND - Ground (Ground)
58 NC - Not connected per congatec; MIPI RFFE data on both 5G modules (Not connected)
59 ANTCTL0 In 1.8 V Antenna tuning control, bit 0, module output (Signal)
60 COEX3 I/O 1.8 V WWAN and Wi-Fi/Bluetooth coexistence, signal 3 (Signal)
61 ANTCTL1 In 1.8 V Antenna tuning control, bit 1 (Signal)
62 COEX_TXD I/O 1.8 V Coexistence serial link. Direction varies by vendor: module input on Quectel, module output on SIMCom (Signal)
63 ANTCTL2 In 1.8 V Antenna tuning control, bit 2 (other use on SIMCom) (Signal)
64 COEX_RXD I/O 1.8 V Coexistence serial link, opposite direction to pin 62 (Signal)
65 ANTCTL3 In 1.8 V Antenna tuning control, bit 3 (other use on SIMCom) (Signal)
66 SIM_DETECT Out 1.8 V SIM presence detect, from the host SIM holder to the module (Signal)
67 RESET# Out 1.8 V Module reset, active low (Signal)
68 SUSCLK Out 3.3 V 32.768 kHz suspend clock; unused by the Quectel, I2C_SDA on the SIMCom (Signal)
69 CONFIG_1 In - Card configuration, bit 1 (Configuration)
70 3.3V / VBAT 3.3 V Supply; WWAN modules accept 3.135 to 4.4 V (Power)
71 GND - Ground (Ground)
72 3.3V / VBAT 3.3 V Supply (Power)
73 GND - Ground (Ground)
74 3.3V / VBAT 3.3 V Supply (Power)
75 CONFIG_2 In - Card configuration, bit 2 (Configuration)

Socket 1, Key E: Wi-Fi and Bluetooth, PCIe x1, USB 2.0, SDIO, UART, PCM

Positions 24 to 31 are removed by the key. UART and PCM are named from the host side: the card transmits on UART_RXD (22) and PCM_IN (12). Module datasheets often print the opposite. Direction seen from the host, the board that carries the socket. Signal names as congatec AN43 reproduces them from the M.2 specification: PER is received by the host, so the card transmits on it.

M.2 (keys M, B and E) · Socket 1, Key E: Wi-Fi and Bluetooth, PCIe x1, USB 2.0, SDIO, UART, PCM. M.2 card edge seen from its top (component) side, contacts pointing down, pin 1 on the right. Top row: odd contacts, top side. Bottom row: even contacts, underside, drawn as if seen through the card..
M.2 card edge seen from its top (component) side, contacts pointing down, pin 1 on the right. Top row: odd contacts, top side. Bottom row: even contacts, underside, drawn as if seen through the card.
Pin Signal Dir. Level Description
1 GND - Ground (Ground)
2 3.3V 3.3 V 3.3 V card supply (Power)
3 USB_D+ I/O - USB 2.0, positive (often Bluetooth) (Differential pair)
4 3.3V 3.3 V 3.3 V card supply (Power)
5 USB_D- I/O - USB 2.0, negative (Differential pair)
6 LED_1# In open drain Status LED 1, active low (Signal)
7 GND - Ground (Ground)
8 PCM_CLK / I2S_SCK I/O 1.8 V PCM or I2S audio clock (Bluetooth) (Signal)
9 SDIO_CLK Out 1.8 V SDIO clock, driven by the host (Signal)
10 PCM_SYNC / I2S_WS I/O 1.8 V PCM frame sync or I2S word select (Signal)
11 SDIO_CMD I/O 1.8 V SDIO command, pulled up to 1.8 V (Signal)
12 PCM_IN / I2S_SD_IN In 1.8 V Audio data received by the host (sent by the card) (Signal)
13 SDIO_DATA0 I/O 1.8 V SDIO data, bit 0 (Signal)
14 PCM_OUT / I2S_SD_OUT Out 1.8 V Audio data sent by the host (Signal)
15 SDIO_DATA1 I/O 1.8 V SDIO data, bit 1 (Signal)
16 LED_2# In open drain Status LED 2, active low (Signal)
17 SDIO_DATA2 I/O 1.8 V SDIO data, bit 2 (Signal)
18 GND - Ground (Ground)
19 SDIO_DATA3 I/O 1.8 V SDIO data, bit 3 (Signal)
20 UART_WAKE# In 3.3 V Card wakes the host for the UART (Bluetooth), open drain (Signal)
21 SDIO_WAKE# In 1.8 V Card wakes the host for SDIO (Wi-Fi), open drain (Signal)
22 UART_RXD In 1.8 V UART received by the host: the card transmits on this pin (Signal)
23 SDIO_RESET# / TX_BLANKING Out 1.8 V Reset of the card SDIO interface, active low (Signal)
32 UART_TXD Out 1.8 V UART sent by the host: the card receives on this pin (Signal)
33 GND - Ground (Ground)
34 UART_CTS In 1.8 V Flow control, host CTS input (card RTS) (Signal)
35 PETp0 Out - PCIe transmitted by the host, positive (Differential pair)
36 UART_RTS Out 1.8 V Flow control, host RTS output (card CTS) (Signal)
37 PETn0 Out - PCIe transmitted by the host, negative (Differential pair)
38 VENDOR_DEFINED - Defined by the card vendor (Signal)
39 GND - Ground (Ground)
40 VENDOR_DEFINED - Defined by the card vendor (Signal)
41 PERp0 In - PCIe transmitted by the card, positive (Differential pair)
42 VENDOR_DEFINED - Defined by the card vendor (Signal)
43 PERn0 In - PCIe transmitted by the card, negative (Differential pair)
44 COEX3 I/O 1.8 V Radio coexistence, signal 3 (Signal)
45 GND - Ground (Ground)
46 COEX_RXD In 1.8 V Radio coexistence, received by the host (sent by the card) (Signal)
47 REFCLKp0 Out - PCIe reference clock, positive (Differential pair)
48 COEX_TXD Out 1.8 V Radio coexistence, sent by the host (Signal)
49 REFCLKn0 Out - PCIe reference clock, negative (Differential pair)
50 SUSCLK Out 3.3 V 32.768 kHz suspend clock supplied by the host (Signal)
51 GND - Ground (Ground)
52 PERST0# Out 3.3 V PCIe reset of the card, active low (Signal)
53 CLKREQ0# I/O 3.3 V Reference clock request, open drain (Signal)
54 W_DISABLE2# Out 3.3 V Bluetooth off, active low (Signal)
55 PEWAKE0# I/O 3.3 V PCIe wake request from the card, open drain (Signal)
56 W_DISABLE1# Out 3.3 V Wi-Fi off, active low (Signal)
57 GND - Ground (Ground)
58 I2C_DATA I/O 1.8 V I2C data (Signal)
59 RESERVED / PETp1 - Reserved, or second PCIe port sent by the host, positive (Not connected)
60 I2C_CLK Out 1.8 V I2C clock, driven by the host (Signal)
61 RESERVED / PETn1 - Reserved, or second PCIe port sent by the host, negative (Not connected)
62 ALERT# In 1.8 V I2C alert from the card to the host, active low (Signal)
63 GND - Ground (Ground)
64 RESERVED - Reserved (Not connected)
65 RESERVED / PERp1 - Reserved, or second PCIe port sent by the card, positive (Not connected)
66 UIM_SWP / PERST1# - SWP line to the SIM (NFC), or reset of the second PCIe port (Signal)
67 RESERVED / PERn1 - Reserved, or second PCIe port sent by the card, negative (Not connected)
68 UIM_POWER_SNK / CLKREQ1# - SIM power for NFC (sink), or clock request of the second PCIe port (Signal)
69 GND - Ground (Ground)
70 UIM_POWER_SRC / GPIO_1 / PEWAKE1# - SIM power for NFC (source), GPIO, or wake of the second PCIe port (Signal)
71 RESERVED / REFCLKp1 - Reserved, or second PCIe port clock, positive (Not connected)
72 3.3V 3.3 V 3.3 V card supply (Power)
73 RESERVED / REFCLKn1 - Reserved, or second PCIe port clock, negative (Not connected)
74 3.3V 3.3 V 3.3 V card supply (Power)
75 GND - Ground (Ground)
An interface to design?

An NVMe SSD, a 4G/5G modem or a Wi-Fi module to integrate over M.2? We have developed several products that carry M.2 cards, NVMe (PCIe) and SSD, and we validate the PCIe, SATA and USB links in our lab.

PET or PER: reading pair direction without a mistake

The most expensive M.2 trap is a vocabulary problem. The congatec table, which follows the specification, names the PCIe pairs from the host point of view: the card transmits on PERn0/PERp0 (pins 41/43) and receives on PETn0/PETp0 (47/49). The Intelligent Memory and UD info SSD datasheets, or the SIMCom SIM8200EA-M2 module, print PETn0 on pin 41 instead, because they speak from the card side.

The electrical assignment does not change: every source we checked puts the card transmitter on 41/43 (Quectel RM520N-GL: PCIE_TX on 41/43; Seeed Jetson carrier table: host receive on 41/43). Before routing, we therefore check each pair from the direction column, never from the name alone. The same flip affects the Key E UART and PCM: Embedded Artists calls pin 22 UART TXD, which congatec and Panasonic call UART RXD.

Another SATA trap: the positive B pair (SATA-B+) shares pin 41 with PERn0, a negative pin in PCIe. The Apacer P201-M SATA SSD datasheet confirms the placement: host receive positive on 41, negative on 43, host transmit negative on 47, positive on 49.

Keys B, M and E: what fits which socket

The key is a notch in the card that matches a ridge in the connector. A B+M card has both notches: the Apacer datasheet states it therefore plugs into a Key B socket as well as a Key M socket. A Key M only card, typical of PCIe x4 NVMe SSDs, does not fit a Key B socket.

The pinout explains what a B+M card can do: the Key B socket only wires PCIe lanes 0 and 1 (41 to 49 and 29 to 37), while the Key M socket wires four. A B+M card therefore runs SATA or PCIe x2 at most. Key E, finally, is for connectivity cards: Embedded Artists describes its Wi-Fi and Bluetooth module as a 2230-D5-E.

On a Key B socket, the host reads CONFIG_0 to CONFIG_3 (pins 21, 69, 75 and 1) to learn which interface the card uses: each pin is grounded or left open on the card, with a pull-up on the host, readable even with the card unpowered. Four grounds mean a SATA SSD, four high pins mean no card (congatec AN43 decode table). The SIMCom SIM8200EA-M2 module grounds CONFIG_0, CONFIG_1 and CONFIG_2 and leaves CONFIG_3 open: WWAN over PCIe and USB 3.

The Key M socket has no CONFIG pins: it relies on PEDET (pin 69). Per the Linux kernel documentation, which cites the M.2 specification r4.0, PEDET low means a SATA card and high means a PCIe card. A socket that only handles NVMe will never run an M.2 SATA SSD, even though it fits mechanically.

Sizes 2230, 2242, 2280 and connector heights

An M.2 card name gives its width then its length in millimeters, then the component height class and the key. Embedded Artists spells out 2230-D5-E: 22 mm wide, 30 mm long, components up to 1.5 mm on both sides, Key E. A 2242 card is therefore 22 × 42 mm and a 2280 is 22 × 80 mm, the size of the Intelligent Memory NVMe SSD. Modems are wider: 30 × 42 mm for the Quectel EM05, 30 × 52 mm for the RM520N-GL.

The connector follows the card thickness. TE Connectivity gives a 2.25 mm height for cards with components on one side and 3.2 mm for double-sided cards, at 0.5 mm pitch. The far end of the card is screwed to a standoff or threaded insert: Panasonic calls for an M2.5 × 4 screw and a card parallel to the host board. We therefore pick the connector height and the standoff height together, for the card length planned.

The notch is off center. On the UD info M2P-80DE (Key M) and Apacer P201-M (B+M) SSD drawings, each notch is 1.20 ± 0.05 mm wide; the Key M notch axis sits 6.125 mm from the card axis, the Key B notch axis 5.625 mm on the other side. These dimensions fall exactly in the middle of positions 59 to 66 and 12 to 19, at 0.25 mm per pin number. The 42 mm length of a 2242 card comes from the ADATA IM2S3334 datasheet.

M.2 cards 22 mm wide to scale, seen from the top side, contacts at the bottom (pin 1 on the right, as in the tables): Key M and Key B notches at their real position. 2230, Key M22 × 30 mm Key M (59-66) 2242, Key B+M22 × 42 mm Key M (59-66)Key B (12-19) 2280, Key M22 × 80 mm Key M (59-66)
M.2 cards 22 mm wide to scale, seen from the top side, contacts at the bottom (pin 1 on the right, as in the tables): Key M and Key B notches at their real position. Width 22 mm and 1.20 mm notches at 6.125 mm (M) and 5.625 mm (B) from the axis: UD info M2P-80DE and Apacer P201-M drawings. Lengths: 30 mm Embedded Artists 2EL, 42 mm ADATA IM2S3334, 80 mm UD info and Apacer. Notch depth not dimensioned: schematic drawing.

3.3 V supply and 1.8 V logic levels

Key M and Key E sockets take 3.3 V only (nine pins on Key M, four on Key E). The Key B socket reads 3.3V/VBAT: the Quectel and SIMCom 4G/5G modules accept 3.135 to 4.4 V and draw large current bursts when they transmit. For the RM520N-GL, Quectel asks for a supply able to deliver 3.0 A continuously, two 220 µF low-ESR capacitors and a VCC trace at least 3 mm wide; SIMCom gives 2.7 A peak for the SIM8200EA-M2.

Sideband signals do not all share one level. Per congatec, PERST#, CLKREQ#, PEWAKE#, SUSCLK, W_DISABLE# and the LEDs are 3.3 V; SMBus, I2C, ALERT#, UART, PCM, SDIO, COEX and the Key B GPIOs are 1.8 V. Connecting a 3.3 V processor GPIO to a 1.8 V module pin needs a level shifter.

PERST#, CLKREQ#, PEWAKE#, SUSCLK and W_DISABLE#

PERST# is the PCIe functional reset, driven by the host. CLKREQ# and PEWAKE# are open-drain outputs of the card: SIMCom requires an external pull-up on the host, and Quectel notes their level depends on the host pull-up voltage. Per UD info, CLKREQ# also serves the L1 power-management substates. Quectel advises driving active-low inputs from a push-pull GPIO rather than a pull-down resistor, to avoid a divider with the module internal pull-up.

SUSCLK is a 32.768 kHz suspend clock supplied by the host to the card (Linux kernel documentation). Embedded Artists rates it "always needed" for its Wi-Fi and Bluetooth module: plan a 3.3 V 32.768 kHz oscillator. Beware on Key B: SIMCom reuses pin 68 as I2C_SDA.

W_DISABLE1# turns Wi-Fi off and W_DISABLE2# turns Bluetooth off on Key E; on Key B, W_DISABLE1# puts the modem in airplane mode. These inputs are active low: the Quectel and SIMCom modules pull them up internally. FULL_CARD_POWER_OFF# does the opposite: both modules pull it down, so a modem whose host leaves that pin floating never starts.

Routing the PCIe lanes of an M.2 socket

For PCIe, Quectel sets 85 Ω ± 10 % differential impedance, intra-pair length matching under 0.7 mm and a total length under 200 mm; for USB 2.0 and USB 3, 90 Ω. The coupling capacitors sit at the transmitter: those of the module transmitter are inside the module, those of the host transmitter go near the host. The differential impedance calculator gives the trace geometry for your stack-up.

On Key M, lane 0 is on 41 to 49 and lane 3 near pin 5; the physical lane order must match the controller, unless it supports lane reversal. We then measure the eye diagrams on our Tektronix oscilloscope with TekExpress, which covers PCI Express, SATA and USB compliance.

Frequently asked questions

FAQ

What is the difference between M.2 Key B and Key M?
The notch position and the signals. Key M (positions 59 to 66 removed) wires four PCIe lanes or SATA, for SSDs. Key B (12 to 19 removed) wires two PCIe lanes, USB 2.0 and 3, SATA, the SIM and GPIOs, for 4G/5G modems and some SSDs.
Does a B+M M.2 SSD fit a Key M socket?
Yes: with both notches, a B+M card plugs into a Key B socket as well as a Key M socket. It runs SATA or PCIe x2 at most. The reverse is not true: a Key M only SSD does not fit a Key B socket.
What voltage powers an M.2 connector?
3.3 V on Key M and Key E. On Key B, the specification allows 3.3V/VBAT: the Quectel and SIMCom WWAN modules accept 3.135 to 4.4 V. Control signals are 3.3 V or 1.8 V depending on the pin.
Why does my M.2 4G/5G modem not start?
Check FULL_CARD_POWER_OFF# (pin 6) first: the Quectel and SIMCom modules pull it down, so it must be driven high. Then the supply: an RM520N-GL needs at least 3.0 A continuous. Finally W_DISABLE1# (pin 8), which puts the modem in airplane mode when low.
Why does an M.2 SATA SSD not work in my NVMe socket?
Because the socket only connects pins 41 to 49 to a PCIe controller. A SATA card grounds PEDET (pin 69) to signal its protocol, but the host must also have a SATA controller on those pins.
Sources

Tables built from these documents and cross-checked against manufacturer datasheets. Always check the datasheet of the connector you actually use: some manufacturers number differently.

Further reading

Other pinouts