DDR4 pinout: 288-pin DIMM and 260-pin SO-DIMM

Contact layout and key notch position

288-pin DIMM: a 133.35 mm board, 144 contacts per side at 0.85 mm pitch. The front carries pins 1 to 144, the back pins 145 to 288, with pin 145 behind pin 1. The key notch is off-centre: the Micron and Samsung dimensions (64.60 mm then 56.10 mm either side of the notch) give 77 contacts on one side and 67 on the other. It therefore falls between pins 77 and 78 on the front, and between 221 and 222 on the back.

The DDR4 DIMM edge is not straight: on the Samsung drawing the contacts in the central zone are 2.6 mm tall and those at the ends 2.1 mm, the transition spreading over about ten millimetres near each end (details C and D of the drawing).

260-pin SO-DIMM: a 69.60 mm board, 130 contacts per side at 0.5 mm pitch, odd pins on the front and even pins on the back. The dimensions (35.50 mm and 28.50 mm) put 72 contacts on the pin 1 side and 58 on the other: the key notch sits between pins 143 and 145 on the front, and between 144 and 146 on the back.

Power rails: VDD 1.2 V, VPP 2.5 V, VTT and VREFCA

According to Micron, VDD is 1.2 V nominal and also powers the I/O (VDDQ is tied to VDD on the module). VPP, at 2.5 V (-0.125 V / +0.250 V), is the DRAM activating supply and must stay greater than or equal to VDD at all times, power-up included. The DIMM has five VPP pins, the SO-DIMM two.

VTT terminates the command, address and control lines at the end of the chain; it is VDD/2, which is 0.6 V per Samsung. VREFCA is the threshold for the command and address inputs; Micron requires it never to exceed 0.6 x VDD.

SPD, temperature sensor and SA0 to SA2 addresses

Every module carries an SPD EEPROM (EE1004, the JEDEC device Micron refers to), often combined with a temperature sensor, on an I2C bus (SCL, SDA) powered by VDDSPD at 2.5 V. The controller reads the module type and timings from it: SPD byte 3, for instance, gives the module type (UDIMM on the Advantech data sheet).

The SA0, SA1 and SA2 pins set the I2C address range of the SPD and sensor. With several slots on the same bus, we wire a different combination for each socket on the host board. Micron also notes that an I2C clock above 100 kHz may require VDDSPD at or below 2.2 V.

EVENT_n flags a thermal threshold crossing and has no function on a module without a sensor. ALERT_n flags a CRC or command/address parity error; PARITY carries the parity computed by the controller when the feature is enabled in MR5.

Fly-by topology: what the pinout means for routing

DDR4 modules use a fly-by topology (Micron data sheets): clock, address, command and control run as a chain from one DRAM to the next, then terminate on VTT at the far end. Data, on the other hand, is point to point, one byte and its DQS_t/DQS_c pair per device. Each DRAM therefore sees the clock with a different delay, while its data arrives over a direct path.

On the host board we therefore treat each byte lane (8 DQ, DM_n/DBI_n and its DQS pair) as a length-matched group, and the CK_t/CK_c and DQS pairs as controlled-impedance differential pairs. Within a byte, bits do not necessarily follow the device order: the Micron DQ map, for example, connects DQ0 of device U1 to module DQ3 (pin 157).

UDIMM or RDIMM: the pins that change

On an RDIMM, address, command and clock enter a register that fans them out to the DRAMs (Samsung data sheet). The pinout stays largely that of the UDIMM; the differences are in the RDIMM column: the DM_n/DBI_n pins and their NC neighbours become the DQS9 to DQS17 strobes of x4-DRAM modules (TDQS for x8), pin 234 becomes A17, and pins 93, 235 and 237 carry the C0 to C2 chip IDs of stacked DRAM.

Kingston points out that in DDR4, unlike DDR5, UDIMM and RDIMM share the same key position. An RDIMM therefore physically fits a slot designed for UDIMMs: it is the memory controller, which reads the module type from the SPD, that must support registered modules.

Why DDR3, DDR4 and DDR5 modules are not interchangeable

A DDR3 DIMM has 240 contacts against 288 for DDR4 (TE Connectivity): the board has neither the same contact row nor the same key. The DDR5 DIMM keeps 288 contacts, but Kingston states that the notch is moved to prevent a DDR4 module going in, and the DDR5 SO-DIMM moves to 262 contacts. Voltages differ too: 1.2 V for DDR4, 1.1 V for DDR5 with a regulator (PMIC) on the module. The key therefore protects the module as much as the host board.

All three DIMMs are 133.35 mm long; only the notch tells them apart by eye. On the data sheet drawings, seen from the front with pin 1 on the left, the notch centre is 54.68 mm from the left edge on DDR3 (Micron), 72.25 mm on DDR4 (Micron) and 68.10 mm on DDR5 (ADATA and Advantech). The offset ranges from 4.15 mm (DDR4 against DDR5) to 17.57 mm (DDR4 against DDR3). The DDR4 SO-DIMM, about half as long, has its notch 38.3 mm from the edge.