DDR5 pinout: 288-pin DIMM and 262-pin SO-DIMM

Reading the pin map: sides, key and subchannels

On a DDR5 DIMM, UDIMM or RDIMM, pins 1 to 144 are on the front side and pins 145 to 288 on the back, with pin 145 opposite pin 1. The vendor tables put the key between pins 75 and 76, that is 219 and 220 on the back.

The key also splits the two subchannels. On a UDIMM, subchannel A takes pins 9 to 73 and 154 to 217, subchannel B pins 78 to 141 and 222 to 286. Pins 1 to 8 and 145 to 152 group the PMIC supply and the sideband bus; RESET_n (95) and ALERT_n (200) are shared.

The SO-DIMM numbers differently: odd pins on the front, even pins on the back. The key falls between pins 125 and 127 on the front (126 and 128 on the back), but the subchannel boundary is elsewhere: A on pins 11 to 134, B on pins 137 to 260, supply and sideband on 1 to 8.

The key is not centred. On the DIMM its axis is 68.10 mm from the left edge, 1.425 mm right of the module centre; on the SO-DIMM it is at 33.55 mm, 1.25 mm left of centre. Seen from the front with pin 1 on the left, a module turned the wrong way round cannot go in.

The PMIC is on the module: the board supplies 5 V, not 1.1 V

The DDR5 connector carries no VDD, VDDQ or VPP pin. A PMIC on the module takes VIN_BULK, 5 V nominal on UDIMM and SO-DIMM according to Micron, and produces VDD and VDDQ at 1.1 V, VPP at 1.8 V, plus two 1.8 V and 1.0 V LDOs, the 1.8 V one feeding the SPD hub.

On the board side we therefore plan a clean 5 V input, the PWR_EN control (active high) and a read of PWR_GOOD, an open-drain output that needs a pull-up. PWR_GOOD is also an input: driving it low turns off the PMIC switching regulators, while the LDOs stay on.

The RDIMM changes voltage: VIN_BULK is 12 V nominal there (4.25 V to 15 V in the Advantech datasheet), a 3.3 V VIN_MGMT input is added, and the PCAMP pin (write protect, Fail_n, power good status) takes the place of PWR_GOOD; there is no PWR_EN.

Two independent 32-bit subchannels

A DDR5 module does not expose a 64-bit bus but two subchannels, suffixes _A and _B: Micron specifies two 32-bit subchannels without ECC, or 36-bit with ECC. Each has its own clocks, command/address and chip selects, and the controller drives them separately.

On UDIMM and SO-DIMM, each subchannel carries CA[12:0], CS0_n and CS1_n (two ranks), two clock pairs CK0 and CK1, DQ[31:0], DM[3:0]_n, five DQS pairs and CB[3:0]. On an RDIMM, commands go through a register driver: CA[6:0] and PAR per subchannel, a single CK pair, CB[7:0] and ten DQS pairs for x4 DRAMs.

The SPD hub and the I3C sideband bus

HSCL and HSDA form the sideband bus to the module’s SPD hub, in I3C Basic or I2C. In the Micron modules, the hub holds the 1024-byte SPD memory and a temperature sensor. In open-drain mode, the pull-ups sit on the motherboard.

Micron gives 1.8 V or 1.0 V levels on these two lines, not 3.3 V: a 3.3 V controller needs a level translator. HSA sets the hub address: the motherboard ties it to ground through a resistor whose value identifies the slot.

On-die ECC and module ECC are two different things

DDR5 chips include on-die ECC (ATP lists it among the DDR5 features). It corrects errors inside the chip and appears on no connector pin. It therefore does not protect the transfer between the module and the controller.

System ECC goes through the CB pins: CB[3:0] per subchannel on UDIMM and SO-DIMM (36 bits), CB[7:0] on RDIMM (40 bits, of which only CB[3:0] are used in EC4 mode according to Rorke). On a non-ECC module these pins stay in the pin map but are not used: you need an ECC module and a controller that handles those bits.

Why DDR4 and DDR5 are not interchangeable

A DDR4 DIMM and a DDR5 DIMM both have 288 pins, but ATP points out that the key is not in the same place and the pin map has changed: a DDR5 module does not fit a DDR4 socket. Power differs too: DDR5 takes 5 V (12 V for an RDIMM) and regulates on the module. Our DDR4 vs DDR5 comparison covers voltages and data rates.

Even within DDR5, UDIMM and RDIMM are not electrically compatible: DQ0_A is on pin 9 on a UDIMM and on pin 7 on an RDIMM, command/address has a different width, and VIN_BULK goes from 5 V to 12 V. A board is designed for one or the other.