What is the difference between JTAG and SWD?

JTAG (IEEE 1149.1) is a multi-vendor 4 or 5-wire standard that can chain several parts. SWD is Arm’s 2-wire debug interface (SWCLK, SWDIO), which shares the TCK and TMS pins. On a Cortex-M, SWD is enough to program and debug.

How do you connect a 20-pin probe to a 10-pin header?

With a 20-pin 2.54 mm to 10-pin 1.27 mm adapter, sold by the probe makers. The wiring is not pin to pin: VTref, SWDIO, SWCLK, SWO and nRESET change numbers (1, 7, 9, 13 and 15 on the 20-pin side; 1, 2, 4, 6 and 10 on the 10-pin side).

What is the VTref pin for?

It gives the probe the target’s I/O voltage, so its buffers drive the signals at the right level (1.8 V, 3.3 V or 5 V). It does not power the board. Without it, most probes refuse to connect.

Should JTAG be disabled on a production product?

On a connected product, yes, or at least protect it. An open debug port lets someone extract the firmware and secrets. Microcontrollers offer read-protection levels or fuses that lock it, sometimes irreversibly.

Pinout

JTAG and SWD pinout: Arm debug headers

JTAG uses four mandatory signals (TCK, TMS, TDI, TDO) and SWD, Arm’s two-wire equivalent, uses only two (SWCLK, SWDIO), on the same pins. Three headers dominate: the 20-pin Arm JTAG at 2.54 mm pitch, the 10-pin Cortex Debug at 1.27 mm pitch and its 20-pin version with ETM trace.

By Hugues Orgitello · Updated October 14, 2026 ·

Cortex Debug, 10 pins, 1.27 mm pitch

The most common header on recent Cortex-M boards. SWD name first, then JTAG, when a pin carries both. Pin 7 is removed to act as a key.

Male header seen from above the PCB, pin 1 square at bottom left

Pin	Signal	Dir.	Description
1	VTref		Target reference voltage, read by the probe to set its logic levels (Power)
2	SWDIO / TMS	I/O	Bidirectional SWD data, or JTAG mode select (Signal)
3	GND		Ground (Ground)
4	SWCLK / TCK	In	Debug clock, driven by the probe (Signal)
5	GND		Ground (Ground)
6	SWO / TDO	Out	SWO trace output, or JTAG data out (Signal)
7	KEY		No pin (key) (Not connected)
8	NC / TDI	In	JTAG data in, unused in SWD (Signal)
9	GNDDetect		Ground, lets the target detect the probe (Ground)
10	nRESET	I/O	Target reset, active low (Signal)

Cortex Debug + ETM, 20 pins, 1.27 mm pitch

Pins 1 to 10 repeat the 10-pin header; pins 11 to 20 add 4-bit parallel ETM trace.

Male header seen from above the PCB, pin 1 square at bottom left

Pin	Signal	Dir.	Description
1	VTref		Target reference voltage, read by the probe to set its logic levels (Power)
2	SWDIO / TMS	I/O	SWD data or TMS (Signal)
3	GND		Ground (Ground)
4	SWCLK / TCK	In	Debug clock (Signal)
5	GND		Ground (Ground)
6	SWO / TDO	Out	SWO trace or TDO (Signal)
7	KEY		No pin (key) (Not connected)
8	NC / TDI	In	TDI in JTAG (Signal)
9	GNDDetect		Probe-detect ground (Ground)
10	nRESET	I/O	Target reset, active low (Signal)
11	GND / TgtPwr+Cap		Ground, or target power from the probe (Ground)
12	TRACECLK	Out	ETM trace clock (Signal)
13	GND / TgtPwr+Cap		Ground, or target power from the probe (Ground)
14	TRACEDATA0	Out	Trace data, bit 0 (Signal)
15	GND		Ground (Ground)
16	TRACEDATA1	Out	Trace data, bit 1 (Signal)
17	GND		Ground (Ground)
18	TRACEDATA2	Out	Trace data, bit 2 (Signal)
19	GND		Ground (Ground)
20	TRACEDATA3	Out	Trace data, bit 3 (Signal)

Arm JTAG 20 pins, 2.54 mm pitch

The legacy header of J-Link and ULINK probes and many evaluation boards. Every even pin from 4 to 20 is ground on the target side. Careful: SEGGER states that pins 14 to 20 on a J-Link are reserved and not necessarily grounded inside the probe.

Male header seen from above the PCB, pin 1 square at bottom left

Pin	Signal	Dir.	Description
1	VTref		Target reference voltage, read by the probe to set its logic levels (Power)
2	Vsupply		Optional supply per Arm; not connected in most probes (Power)
3	nTRST	In	JTAG logic reset, active low, optional (Signal)
4	GND		Ground (Ground)
5	TDI	In	JTAG data in (Signal)
6	GND		Ground (Ground)
7	TMS / SWDIO	I/O	JTAG mode select, or SWD data (Signal)
8	GND		Ground (Ground)
9	TCK / SWCLK	In	Debug clock (Signal)
10	GND		Ground (Ground)
11	RTCK	Out	Return clock, for adaptive clocking (Signal)
12	GND		Ground (Ground)
13	TDO / SWO	Out	JTAG data out, or SWO trace (Signal)
14	GND		Ground (Ground)
15	nRESET	I/O	Target system reset, active low (also called nSRST) (Signal)
16	GND		Ground (Ground)
17	NC		Not connected (formerly DBGRQ) (Not connected)
18	GND		Ground (Ground)
19	NC		Not connected (formerly DBGACK; some probes supply 5 V here) (Not connected)
20	GND		Ground (Ground)

Tag-Connect TC2030 (SWD), 6 pads

Connector-less footprint: the spring-pin cable presses onto six PCB pads. Assignment of the TC2030-CTX cable for the 10-pin Cortex header.

Footprint seen from above the PCB (top layer); the cable’s alignment holes set the orientation

Pin	Signal	Dir.	Description
1	VTref		Target reference voltage, read by the probe to set its logic levels (Power)
2	SWDIO	I/O	SWD data (Signal)
3	nRESET	I/O	Target reset, active low (Signal)
4	SWCLK	In	SWD clock (Signal)
5	GND		Ground (Ground)
6	SWO	Out	SWO trace (Signal)

An interface to design?

A board to make debuggable and testable in production, then locked before shipping? We design the debug port, the programming bench and the protection strategy.

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JTAG or SWD?

On a Cortex-M, SWD does everything development needs (programming, breakpoints, memory reads) with two wires, plus SWO for printf-style trace. JTAG stays useful to chain several parts on one interface (FPGA, CPLD, processor) and for production boundary-scan testing (IEEE 1149.1).

The most common design mistakes

VTref left unconnected. The probe reads VTref to set its levels. Left floating, the probe does not detect the target, or drives its signals at the wrong voltage. VTref goes to the microcontroller’s I/O supply, not to the board input.

nRESET not wired. Without it, the probe cannot regain control of firmware that disables the SWD pins or goes into deep sleep at startup. Keep a pull-up (often 10 kΩ) and a modest capacitor.

Debug port left open in production. An accessible JTAG or SWD port lets anyone read out the firmware and keys. On a connected product, lock it (read-protection levels, debug fuses) before shipping: the Cyber Resilience Act expects it too.

Frequently asked questions

FAQ

What is the difference between JTAG and SWD?: JTAG (IEEE 1149.1) is a multi-vendor 4 or 5-wire standard that can chain several parts. SWD is Arm’s 2-wire debug interface (SWCLK, SWDIO), which shares the TCK and TMS pins. On a Cortex-M, SWD is enough to program and debug.
How do you connect a 20-pin probe to a 10-pin header?: With a 20-pin 2.54 mm to 10-pin 1.27 mm adapter, sold by the probe makers. The wiring is not pin to pin: VTref, SWDIO, SWCLK, SWO and nRESET change numbers (1, 7, 9, 13 and 15 on the 20-pin side; 1, 2, 4, 6 and 10 on the 10-pin side).
What is the VTref pin for?: It gives the probe the target’s I/O voltage, so its buffers drive the signals at the right level (1.8 V, 3.3 V or 5 V). It does not power the board. Without it, most probes refuse to connect.
Should JTAG be disabled on a production product?: On a connected product, yes, or at least protect it. An open debug port lets someone extract the firmware and secrets. Microcontrollers offer read-protection levels or fuses that lock it, sometimes irreversibly.

Sources

Arm, Cortex-M Debug Connectors
SEGGER Knowledge Base, 20-pin J-Link Connector
Tag-Connect, TC2030-CTX datasheet
IEEE 1149.1, Standard Test Access Port and Boundary-Scan Architecture (paid or members-only document)

Tables built from these documents and cross-checked against manufacturer datasheets. Always check the datasheet of the connector you actually use: some manufacturers number differently.