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AESTECHNO
Hammerstad-Jensen

PCB Trace Impedance Calculator

To calculate PCB trace impedance, pick the geometry (microstrip or stripline), then enter trace width, copper thickness, dielectric height and the laminate's relative permittivity (Er). The calculator applies the accurate Hammerstad-Jensen (microstrip) and Wheeler-Cohn (stripline) closed forms to return single-ended characteristic impedance in ohms. It also handles the trapezoidal trace cross-section (etch back ΔW), soldermask coating, the inverse solve (target impedance to width) and signal loss (conductor, dielectric, insertion). For differential pairs, use our differential-pair calculator.

Inputs

Model

Model
Solve for

Compute impedance from geometry, or find the trace width for a target impedance.

Length unit

Widths and heights are entered in this unit (the math normalises to mm).

Trace

We find the trace width that yields this impedance (other parameters fixed).

Finished copper thickness: 1/4 oz ≈ 0.009 mm · 1/2 oz ≈ 0.018 mm · 1 oz ≈ 0.035 mm · 2 oz ≈ 0.070 mm · 3 oz ≈ 0.105 mm.

Trapezoidal cross-section (bottom W, top W1) from etch back. Effective width = W - ΔW/2. By copper weight: 1/4 oz and 1/2 oz ~0.013 mm (0.5 mil); 1 oz ~0.025 mm (1 mil); 2 oz ~0.076 mm (3 mil); 3 oz ~0.15 mm (6 mil); 4 oz ~0.18 mm (7 mil). 0 = vertical walls.

Dielectric

Microstrip: dielectric height H below the trace. Stripline: plane separation B.

Typical FR-4: 4.2 to 4.6 (use the laminate datasheet).

Soldermask coating

A soldermask over the trace raises effective Er and lowers Z0 (~3%).

Coating thickness over the trace. Typical LPI soldermask 12 to 25 um.

Soldermask permittivity. Typical LPI 3.2 to 4.0.

Signal loss

Signal loss

Conductor (skin-effect + roughness) and dielectric (tan delta) loss, in dB/inch.

FR-4 ~0.02; Rogers/PTFE 0.001 to 0.004 (laminate datasheet).

RMS copper roughness. VLP ~0.5; HVLP ~0.3; standard foil 1 to 2 um.

Length used for the total insertion loss and S-parameters (in inches).

System impedance for S11 (return loss) and S21 (insertion loss). 50 Ohm typical; 75 Ohm video/RF.

Ground plane Dielectric · εr Copper trace W1 W T H

Cross-section (not to scale)

Result

49.8 Ω

Breakdown

Effective εr 3.2
Propagation delay 5.966 ps/mm · 151.5 ps/in
Capacitance / length 0.1199 pF/mm
Inductance / length 0.2969 nH/mm

Email me this result

You receive the result with its direct link. Our design house gets a copy and can react to it, simply reply if you want an engineer's eye on it.

Hammerstad-Jensen (microstrip) / Wheeler-Cohn (stripline) closed forms, accurate to ~1% of a 2D field solver. Still sign off production stack-ups with a field solver and a fab controlled-impedance coupon.

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Frequently asked questions

FAQ

What is the difference between microstrip and stripline impedance?
A microstrip routes on an outer layer with the dielectric and reference plane on one side only, so its field partly travels through air. A stripline is buried between two reference planes, fully embedded in dielectric. For the same width and Er, stripline gives lower impedance and tighter, more predictable control, while microstrip is faster to route and easier to probe.
Why is 50 ohm the default single-ended target?
50 ohm is a practical compromise: on typical FR-4 geometries it balances conductor loss (favouring higher impedance) against power handling and dielectric loss (favouring lower impedance), and it matches the reference impedance of most connectors, test gear and SerDes I/O. Many differential pairs target 90 or 100 ohm instead, so always check the interface spec (USB, Ethernet, PCIe, HDMI) before routing.
What Er value should I use for FR-4?
FR-4 is a class of glass-weave laminates, not a single material, so its relative permittivity (Er) is not fixed. It typically falls around 4.2 to 4.6 at low frequency and drops slightly as frequency rises. For controlled impedance, do not assume a generic 4.5 figure: pull the Er and loss tangent from your fabricator's specific laminate datasheet at the relevant frequency, since glass-resin ratio and resin content shift the value.
How does copper weight affect trace impedance?
Copper weight sets the finished trace thickness (1 oz is roughly 35 micrometres, 2 oz roughly 70). Thicker copper increases the conductor cross-section coupling to the reference plane, which lowers characteristic impedance, and it also enlarges trace-edge fringing and etch undercut. Heavier copper therefore usually needs a slightly narrower or differently spaced trace to hold the same target impedance.
How much do fabrication tolerances shift the calculated impedance?
A calculator gives a nominal value; the board house introduces real variation. Etch width tolerance, dielectric height spread between prepreg and core, copper-weight tolerance and Er variation across a panel all stack up. Real-world controlled-impedance builds are commonly specified at plus or minus 10 percent. Always send your stack-up to the fabricator for a controlled-impedance report rather than trusting the nominal number alone.
Is this as accurate as a 2D field solver (Sierra, Polar, Simbeor)?
No, and it does not claim to be. Fab-house tools numerically solve Maxwell equations in 2D and model the exact trapezoidal cross-section, multi-dielectric stack-ups and high-frequency loss in detail. Our calculator uses accurate quasi-static closed forms (Hammerstad-Jensen, Wheeler-Cohn, Cohn), within about 1 percent of a field solver on common geometries, with first-order corrections for etch back, soldermask and signal loss. It is the right tool for fast, free first-pass sizing; to freeze a critical production build, confirm on a 2D field solver and a fabricator TDR coupon.
Go further

AESTECHNO is an electronics design house based near Montpellier, France, led by engineer Hugues Orgitello with 10+ years in electronic design. We build controlled-impedance, high-speed and RF boards and have a 100% first-pass record on the CE/FCC certifications we have taken to test.