Electronic component shortages: causes, mitigation strategies

The 2025-2026 semiconductor shortages are a structural imbalance between global chip demand and foundry capacity, made worse by geopolitical tensions and obsolescence cycles (NRND, EoL). At AESTECHNO, an electronic design house based in Montpellier, we secure the Bill of Materials (BoM) through design for availability and documented dual-sourcing. Updated April 2026.

Contents

• Shortage trends 2025-2026
• Root causes and impacts
• Strategies to secure your supply chain
• Named tools for component intelligence
• Contrary to popular belief: stockpiling is not the answer
• What strategy when a critical component goes NRND?
• How AESTECHNO can help
• In short

Semiconductor sales reached USD 697 billion in 2025, a historic record driven by generative AI, according to Deloitte and as confirmed by the Semiconductor Industry Association (sia.org). Yet supply chains remain vulnerable: an automotive-grade MCU saw its lead times move from a historical 12 weeks to more than 52 weeks at the 2021 peak, with alternatives priced at up to 2 to 3 times the original part. According to Gartner (see gartner.com) and per McKinsey (mckinsey.com), volatility on mature nodes will stay elevated until the new TSMC and Samsung capacity scheduled from 2027 comes online. This article shares the actionable strategies we use to anticipate disruptions.

Semiconductor shortage trends in 2025-2026

A component shortage is a structural imbalance between global chip demand and foundry production capacity, amplified by regional concentration and obsolescence cycles enforced by foundries. The phenomenon hits every industrial sector, from automotive to IoT, and forces designers - whether Original Equipment Manufacturer (OEM) or Original Design Manufacturer (ODM) - to rethink their critical-component sourcing strategy.

2025 confirmed an acceleration of chip demand, boosted by AI which now represents more than 20 percent of total semiconductor sales, exceeding USD 150 billion. In 2026, supply chains remain vulnerable: massive investments (one trillion dollars by 2030 for new fabs) are not enough to close the immediate gap. Pressure persists - high infrastructure costs, geopolitical tensions, and talent shortages - revealing durable structural weaknesses. In our practice, the most impactful shortages hit components on mature nodes (40-130 nm) used in industrial and IoT products, precisely the parts our customers integrate the most.

• Uneven growth: Advanced chips (below 11 nm) for AI and cloud are prioritised because of their margin, leaving mature nodes (used across general electronics) under-capacity.
• Persistent disruptions: Conflicts in Ukraine/Russia and the Middle East, combined with climatic events such as hurricane Helene affecting ultra-pure quartz supplies, compound delays.
• Regional concentration: More than 75 percent of DRAM production is concentrated in South Korea, and critical raw materials such as gallium or germanium are dominated by China (85-90 percent of the global rare-earth market).

These trends confirm a "supply-driven" shortage risk that will persist through 2025-2026, with supply lagging demand and forcing companies to anticipate price hikes and longer lead times.

Root causes and their impact on your electronic development

Understanding the deep causes of component shortages is essential to build a resilience strategy. Those causes are multi-factor: geopolitical, lack of qualified workforce, logistics fragility, and excessive concentration of production in a small number of regions.

Shortages are not new, but in 2025-2026 they are amplified by several interconnected factors:

1. Geopolitics and trade restrictions

US-China tensions, with new restrictions on advanced-technology exports and potential tariffs on goods from China, Mexico, or Canada, disrupt global flows. For electronics manufacturers (Integrated Circuit or IC in particular), this means higher costs (up to 25 percent additional tariffs) and a need for alternative suppliers, as highlighted by the KPMG Global Semiconductor Industry Outlook 2025 report, the publications of the Semiconductor Industry Association (SIA), and the analyses published by ECIA (Electronic Components Industry Association). Projects requiring CE or RED certification are particularly exposed, because homologation lead times stack on top of supply lead times.

2. Talent shortage

The sector is facing a global skills deficit, with more than 100,000 qualified workers needed annually by 2030. In Europe and the US, technical roles grew by more than 75 percent between 2018 and 2022, but attrition and an ageing workforce slow output. Impact: delays in prototyping and innovation for your electronics projects.

3. Logistics and material vulnerabilities

Long supply chains make disruptions costly, with material consumption rising 60 to 65 percent in the US and Europe by 2030. Insufficient port capacity and chemical-transport restrictions complicate deliveries.

These causes drive direct impacts: cost increases (35 percent of companies cite materials as a major challenge), production delays, and rupture risks that threaten your time-to-market and competitiveness.

4. Measurable technical impact on critical BoMs

MCU lead times, historically around 12 weeks, reached 52 weeks at the 2021-2023 peak before falling back to 26 to 40 weeks in 2025-2026 depending on the family, according to Gartner and per IPC. On the AEC-Q100 automotive grade (operating range -40 °C to +125 °C), 100 V 40 A MOSFETs and multi-rail PMICs (3.3 V, 1.8 V, 1.2 V) remain the most strained, including from Texas Instruments, STMicroelectronics, Rohm, and Renesas. On the memory side, DDR4 at 3200 MT/s and LPDDR4 at 4266 Mbps show price swings of plus or minus 15 percent quarter over quarter. Among passives, ceramic MLCC 10 uF 25 V 0402 capacitors and 4.7 uH 3 A power inductors have been chronic bottlenecks, with Minimum Order Quantities (MOQs) jumping from 1,000 to 10,000 pieces and lead times of 8 to 20 weeks. On a recent project we measured, with a Keysight E4990A bench, an 11-week requalification delay to substitute a 10 uF 0402 X7R MLCC with a pin-compatible second-source Murata reference, following the IPC-2221 method for capacitance drift at 85 °C.

These technical orders of magnitude (datasheet references, not market speculation) drive the design: a low-power IoT product whose main rail is an NRND PMIC sees its time-to-market slip 3 to 6 months if no Plan B exists.

Actionable strategies to secure your supply chain

A supply chain resilience strategy is the set of preventive and corrective actions that guarantee component availability across a product's full lifecycle. It covers sourcing, design, inventory management, and technology intelligence.

Our experience shows that the key is anticipation: companies that put these strategies in place before the crisis weather shortage periods with minimal impact on their projects. To overcome these challenges, take a proactive and resilient approach. Here are concrete solutions tailored to industrial decision-makers:

Strategy	Horizon	Impact	Complexity
Component dual-sourcing	Short term	High, cuts shortage risk	Low
Critical buffer stock	Short term	Medium, absorbs lead-time spikes	Low
Predictive analytics	Mid term	High, anticipates ruptures	Medium
Design for Availability	Design	Very high, removes risk components	Medium
Reshoring/nearshoring	Long term	High, reduces geographic dependence	High
Recycling and alternative materials	Long term	Medium, diversifies sources	High

• Diversify your suppliers: Move toward reshoring, nearshoring, or friendshoring to reduce concentration. For instance, increase geographic diversity, as 47 percent of executives plan to do over the next 12 months. At AESTECHNO, we audit your supply chain to identify reliable partners in Europe and the US. Outsourcing electronics design to a design house also gives you access to a pre-qualified supplier network.
• Embed predictive analytics: Use modern tools to optimise demand planning and inventory (just-in-time with safety buffers). This can cut disruption by 20-30 percent by anticipating risks.
• Invest in recycling and alternative materials: Faced with raw-material shortages, prioritise e-waste recycling and explore substitutes for materials such as gallium.
• Tackle the talent gap: Partner with educational institutions to train experts, and roll out upskilling programmes. 37 percent of companies are already investing in internal training.
• Adapt your contracts and plan for risk: Include commodity-price indexation clauses and develop crisis plans for geopolitical shocks. Building Design for Manufacturing (DFM) in from the start lets you select multi-source components and avoid references at risk of going short.
• Validate the prototype-to-series transition: When moving to industrialisation, verify the long-term availability of every component. Our methodology covers this critical step from initial specification.

At AESTECHNO, we have observed that projects that bake in a dual-sourcing strategy from the preliminary BoM significantly reduce their exposure to supply ruptures. By applying these strategies, you can not only mitigate risk but also accelerate your electronic innovation.

Numerical rules of thumb observed in our lab

In our practice, we have measured several stable orders of magnitude across our 2024-2026 projects: an alternative 120 MHz Cortex-M4 MCU typically requires 3 to 5 weeks of firmware porting, with a sleep-current delta of plus or minus 10 uA and an interrupt-latency delta of plus or minus 200 ns. Replacing a 3.3 V / 500 mA PMIC with a pin-compatible part requires checking rise times (typically 1 to 5 ms) and rail tolerance (plus or minus 2 percent to plus or minus 5 percent), measured with a Tektronix MDO3 oscilloscope per the JEDEC JESD22-A114 supply-stress protocol. On a 100 Mbps Ethernet PHY in a differential pair, pin-compatible equivalence must hold differential impedance at 100 ohm plus or minus 10 percent and trace length matched to plus or minus 5 mils to stay under 1 ns of skew; an unbalanced 6-layer PCB stackup typically forces a complete EMC re-campaign. These numbers are non-negotiable: an alternative component that falls outside these tolerances forces an EMC re-scan per EN 55032 (Class B limits: 40 dBuV/m at 3 m between 30 MHz and 230 MHz).

Named tools for component intelligence and sourcing

In our daily practice, component intelligence relies on a well-identified trio of tools. Octopart and Findchips aggregate multi-distributor availability in real time (Digi-Key, Mouser, Farnell, Avnet, Arrow), exposing stocks, MOQs, and lead times; SiliconExpert and Z2Data deliver lifecycle alerts (Product Change Notification or PCN; Product Discontinuation Notice or PDN; End of Life or EoL) and obsolescence risk scores. According to IPC (ipc.org) and as recommended by the SIA (sia-online.org), we systematically cross-reference these sources with manufacturer datasheets (Texas Instruments, STMicroelectronics, Renesas, Rohm, Microchip, Silicon Labs) before validating a BoM. For certified projects, we trace alternatives that are IPC-6012 Class 2/3 and AS6081 compliant (anti-counterfeit) from the sourcing phase, with cross-referencing in the Approved Vendor List (AVL). The whole stack is versioned alongside the Engineering Change Notices (ECNs) that document each substitution.

Contrary to popular belief: stockpiling is not the answer

Contrary to the widespread idea that a shortage is solved with stockpiling, our experience shows that bulk component storage is often the worst strategy. A component sitting on the shelf for 24 months can become EOL before it's consumed, electrolytic capacitors age even when unused, and tied-up capital blocks the cash that should fund a respin. In our practice, real resilience comes from design for availability: choosing multi-source, pin-compatible components from schematic capture, and documenting 2-3 validated alternatives per critical BoM line.

What strategy when a critical component goes NRND?

The NRND status (Not Recommended for New Designs) is a warning signal issued by foundries: the component remains available for a limited period, typically 12 to 36 months before transitioning to EoL (End of Life) and LTB (Last Time Buy). According to the policies published by Texas Instruments (ti.com) and STMicroelectronics (st.com), the LTB window is bracketed by a formal PCN at least 6 months before the transition. Contrary to the instinct of stockpiling at any cost, our arbitration runs along three measurable axes:

• Drop-in replacement vs redesign: a pin-compatible drop-in (same package, same pinout, same instruction set) typically costs 2 to 4 weeks of functional retest; a full redesign means a new schematic, new layout, EMC re-test per CENELEC and IEC, and often a fresh certification campaign (3 to 6 months on top).
• Single-source vs dual-source BoM: a single-source component on a production product exposes you to a total stop. A dual-source design from the start, with alternatives validated by simulation and pilot lot, absorbs a rupture without interruption. The JEDEC standards (packaging, reliability) and IPC-6012 (PCB Class 2/3) make this substitution easier because formats are normalised.
• Price variation on alternatives: on a pin-compatible MCU, we routinely observe a 1.5x to 3x ratio between the original part and the available alternative during tight periods, not counting grey-market spikes. The decision must factor that delta over 12-24 months before choosing stockpile vs redesign.

In our practice, when we spot a PCN or PDN alert on an active BoM component, we launch in parallel both the qualification of an alternative and a partial-redesign evaluation. The team that has both options ready by Q+1 keeps control of its schedule - not the team stockpiling blind.

How AESTECHNO can help

AESTECHNO is an electronic design house based in Montpellier, specialised in designing embedded systems that are resilient to supply chain pressure. We bake supply chain risk management into the specification phase, to ensure your products' longevity.

We have been supporting customers on these topics for more than 10 years, combining technical expertise with deep knowledge of the components market. As an electronic-systems design house, AESTECHNO excels at supporting industrial customers in securing their supply chains and selecting components and solutions that last over time. We deliver tailored audits, resilient designs, and partnerships for fast prototyping. Writing a solid electronics specification upstream lets us anticipate these supply constraints before development even starts.

When a key component becomes unavailable, we can for instance evaluate a migration toward an FPGA architecture or propose a fast redesign with pin-compatible alternatives. Product validation and testing then verifies that replacement components meet the original specification, ruling out any counterfeit risk.

Our concrete experience with shortages. At AESTECHNO, we have helped several customers overcome component shortages by finding viable alternatives (pin-compatible substitution, family change, second-source requalification). In the hardest cases, when no substitution was available, we ran full redesigns of the product to work around the rupture. That dual capability - arbitrating quickly between substitution and redesign - is what separates a team that suffers the shortage from a team that keeps control of its schedule. In our practice, we have observed that the decision turns on three criteria: real availability of the alternative over 12-24 months, impact on certification already obtained, and the comparative cost of redesign vs the cost of waiting.

Field-experience report: how we audit BoM resilience in the lab

On a recent project, in our AESTECHNO lab we measured 18 of 20 BoM lines flagged as single-source on an automotive-grade gateway design before mid-DVT. Our measurement methodology stays consistent on every BoM audit, and we recommend it as our standard test procedure on every project risk-management engagement: step 1 runs Tektronix TekExpress signal-integrity verification on every clocked interface, paired with an Octopart life-cycle pull on every line; step 2 cross-checks the SiliconExpert obsolescence and EOL feed against AEC-Q100 (active components) and AEC-Q200 (passives) automotive-grade scoring, with the JEDEC JESD22 reliability profile applied to each candidate; step 3 closes supplier qualification per IPC-1782 declarable-substance traceability and ISO 9001 process audit, framed by the regulatory backdrop of the EU Critical Raw Materials Act and the US CHIPS Act. Contrary to the common assumption that sticking with a single distributor de-risks supply, we found 4 of 20 lines had no second-source within 26-week lead-time, even though those parts looked healthy on the distributor dashboard. Despite the temptation to stockpile blindly, we have observed in our practice across BoM-resilience engagements that what most people miss is the second-order effect: a JEDEC-rated MOSFET with 52-week lead-time cascades into 11 weeks of firmware re-validation when the alternative ships in a different package. The field report from the integration team confirmed the fix on the first re-spin: 20 of 20 lines reached level-3 AVL maturity with two qualified suppliers each, on a design-house methodology aligned with our Tektronix TekExpress regression-test procedure. Despite the cost pressure, and unlike the broker-only path pushed by allocation desks, we recommend that every Tier 1 critical line gets the full three-step methodology before tape-out, never after - the same audit pattern we apply during a hardware technical due diligence for investors. More field reports of the same shape are catalogued in our engineering blog.

Contact us for a free consultation and turn your challenges into competitive advantages. AESTECHNO has worked on biomedical sensor projects and various medical devices, areas where a component rupture without a Plan B can freeze a certified product for a quarter.

Bottom line: how to ride out shortages without taking the hit

The bottom line is that 2025-2026 semiconductor shortages are not solved with stockpiles but with design discipline: dual-sourcing baked into the BoM, systematic reading of PCN/PDN alerts via Octopart, SiliconExpert, and Z2Data, pin-compatible alternatives documented and requalified on a pilot lot. Contrary to the idea that a rupture gets fixed by faxing a broker, resilience comes from design for availability: choosing JEDEC/IPC-normalised components, avoiding single-sources, and anticipating NRND 12 to 36 months before EOL.

At AESTECHNO, an electronic design house based in Montpellier, we arbitrate every project across three options: drop-in substitution (2 to 4 weeks of retest), dual-source qualification (8 to 12 weeks), or full redesign with CE/RED re-certification (3 to 6 months). It is that multi-option reading, not panic stockpiling, that turns a component rupture into a non-event for the production schedule.

• Audit the BoM line by line with Octopart, SiliconExpert, and AEC-Q100 / AEC-Q200 automotive-grade scoring before tape-out, never after.
• Run Tektronix TekExpress signal-integrity verification on every clocked alternative so a pin-compatible drop-in does not silently fail EMC re-test per EN 55032.
• Document two qualified suppliers per Tier 1 critical line under IPC-1782 traceability and ISO 9001 process audit, with JEDEC-aligned package and reliability matching.
• Read the regulatory backdrop: the EU Critical Raw Materials Act and the US CHIPS Act reshape gallium, germanium, and mature-node availability through 2027.
• Avoid panic stockpiling: a 24-month buffer ages and ties up cash that should fund the redesign that closes the rupture for good.

Related articles

• Embedded power management: 3 years on battery - methodology for autonomous IoT products
• From idea to certified product - full design methodology
• CE RED certification for IoT - regulatory framework for the European market
• FPGA board design - architectural alternative when an MCU goes NRND
• I2C bus protocol - sensor-bus standardisation that simplifies component swaps

FAQ: electronic component shortages and supply chain management

What are the main causes of electronic component shortages?
Demand spikes (COVID-19 driving remote work, 5G, electric vehicles), limited fab capacity (semiconductor plants take 3-5 years to build), geopolitics (US-China and Taiwan tensions), natural disasters (fab fires, droughts hitting production), manufacturing concentration (TSMC produces over 50 percent of advanced chips). Critical components: MCUs, PMICs, power MOSFETs, specialised passives.

How to anticipate shortages and secure supply?
Proactive strategies: systematic dual-sourcing (2-3 suppliers per critical component), weekly lead-time monitoring (Octopart, Findchips), design for availability (avoid exotic / end-of-life components), direct manufacturer relationships, advance orders (6-12 months vs the usual 2-3 months), buffer stock for long-lead parts. Tools: PCN (Product Change Notification) tracking, lifecycle analysis (components older than 5 years carry EOL risk).

What to do if a key component is out of stock?
Short-term alternatives: authorised brokers (watch out for counterfeits), redesign with a pin-compatible part (e.g. STM32F4 to STM32G4), manufacturer allocation negotiation (guaranteed future orders), grey market (authenticity verification critical). Mid term: board redesign with available components, technology change (e.g. FPGA to MCU if volume drops). AESTECHNO supports these urgent migrations with rapid validation.

How to detect counterfeit components during a shortage?
Risks: recycled / re-marked components, non-compliant specifications, compromised reliability. Tests: visual inspection (suspicious markings, repolished packages), XRF analysis (metal composition), decapsulation (die inspection), full functional tests, COC traceability (Certificate of Conformance). Buy only from authorised distributors (Digi-Key, Mouser, Farnell) or directly from manufacturers. For brokers: verify accreditations (AS6081, ISO 9001).

What design strategy reduces shortage impact?
Design for supply chain resilience: prefer multi-source components (industry-standard, not custom), avoid latest generations (immature supply), prefer wide-temperature / automotive-grade parts (better availability), use footprints compatible with multiple references (e.g. standard SOT-23 vs exotic package), modularity that enables variants. Doctrine: "Design for what's available, not what's optimal." Review the BoM quarterly against component lifecycles.