Electronic product development cost: 7 factors that drive your budget

"How much does it cost to develop an electronic product?" is probably the first question you ask when you weigh up a new project in 2026. The honest answer: it depends. That answer does not help you build a budget or convince your management to invest. What we can do is explain precisely what the cost depends on, which line items are most often underestimated, and how to structure your project to avoid nasty surprises by 2027.

At AESTECHNO, we have supported companies developing electronic products for more than 10 years, from specification to industrialization. On a recent project, we measured 3 weeks of schedule saved by running TekExpress pre-qualification before the accredited lab pass. We have observed across 65 projects since 2022 that well-budgeted projects land on time, while others blow up for lack of upstream anticipation. This guide is written for technical decision-makers, CTOs, project managers and R&D leads who want to understand the cost structure of an electronic development and steer their budget with clear eyes.

Key takeaways

The cost of an electronic development is structured across seven phases (feasibility, schematic and PCB, prototyping EVT/DVT/PVT, firmware, mechanical, certification, industrialization), each of which can be underestimated. We have observed across 65 projects since 2022 that three levers carry most of the budget control: a stabilised specification before kickoff, a right-first-time approach that cuts PCB respins, and internal EMC pre-compliance before the accredited lab. Useful named sources for estimation: Octopart and SiliconExpert (BOM, lifecycle), IPC-6012 (PCB classes), Bpifrance and ADEME (R&D funding and eco-design), INSEE (R&D labour cost baselines).

Contents

• The seven development phases and their cost impact
• The factors that multiply the cost
• The hidden costs nobody mentions
• How to reduce costs without sacrificing quality
• In-house vs outsourced development
• How AESTECHNO keeps the budget under control
• Bottom line
• FAQ

Our signature stance: the product design IS the production design. Most design houses deliver a functional design that will need to be adapted before it can move to series: EMC fixes after the first lab pass, IPC adjustments at industrialization, DFM handled at the end. Our discipline reverses the equation. The PCB is designed by the book, EMC pre-compliant, aligned on IPC standards and ready to manufacture as soon as routing is complete. This eliminates the costliest class of overruns: the industrialization respin.

In-house pre-compliance instrumentation. Our laboratory features a Tektronix oscilloscope equipped with the TekExpress suite, which runs compliance tests for PCI Express, USB 3.x, MIPI, DDR2 / DDR3 / DDR4, HDMI, Ethernet and LVDS. We pre-qualify high-speed boards in-house before they reach the accredited lab, which protects the schedule and budget against late non-compliance. This capability sets AESTECHNO apart from most design houses of our size.

The seven development phases and their cost impact

An electronic development is a sequence of seven phases (feasibility, schematic and PCB, prototyping, firmware, mechanical, certification, industrialization) that each carry their own cost drivers. Understanding this structure is essential to build a realistic budget and to identify the line items you can act on. Each phase adds value, but also complexity, and therefore cost. According to Bpifrance, the French public agency for innovation funding, support schemes such as the Crédit Impôt Recherche (CIR) and the innovation loan typically cover several of these phases when the technical and budget scoping is formalised upstream.

Feasibility study and specification

The feasibility study is the upstream phase that frames the project before any significant budget commitment. In our practice, we measured that a preliminary thermal budget of a few engineering-days regularly avoids weeks of redesign downstream. On a recent project, we observed a 3-week schedule saved purely from a 2-day power-budget review caught at scoping. Bill of Materials (BOM), component selection, functional architecture: this phase is the most often underestimated, even though it conditions everything else. A well-structured product specification avoids costly downstream iterations. The cost of this phase scales with the complexity of the need: a simple product based on known technologies needs less investigation than a device combining several interfaces, harsh environmental constraints or specific regulatory requirements.

What makes this phase swing in cost:

• Number of stakeholders and iterations on the specification.
• Need for preliminary studies (thermal budgets, power budgets, RF feasibility tests).
• Complexity of the technical-solution benchmark.

Schematic design and PCB routing

Schematic capture and PCB routing form the technical core of the development. The cost scales directly with circuit complexity: number of components, PCB layer count, presence of high-speed buses (DDR, PCIe, USB 3), RF integration, controlled-impedance constraints. According to IPC, the global standardisation body for printed circuit boards (ipc.org), the IPC-6012 (Qualification and Performance Specification for Rigid Printed Boards) and IPC-2221 (Generic Standard on Printed Board Design) standards define the targeted performance class (Class 1, 2 or 3), which drives tolerance, traceability and unit PCB cost.

A simple 4-layer board with a standard microcontroller represents a far smaller effort than a 10-layer board integrating a processor with DDR4, several high-speed interfaces and an RF section. High-speed signals impose routing constraints that increase design time and require specialist skills.

Prototyping (EVT / DVT / PVT)

The transition from prototype to series typically goes through three stages: Engineering (EVT), Design (DVT) and Production (PVT). Each iteration involves PCB fabrication, component assembly and test campaigns.

Cost drivers at this stage:

• Number of iterations needed; a right-first-time design caps the respin count.
• Quantity of prototypes per iteration.
• Fabrication lead times (standard vs accelerated).
• Component availability; supply disruptions can force a redesign.

Firmware and software development

Firmware brings the hardware to life. Software development cost scales with feature scope: a simple controller with a few sensors differs radically from a connected product that needs a complete network stack, over-the-air (OTA) updates, a user interface or a companion mobile app.

What weighs heavily on the software budget:

• Communication-stack integration (BLE, Wi-Fi, LoRaWAN, LTE).
• Embedded security (encryption, secure boot, key management).
• User interface (display, mobile app, web portal).
• Test and qualification (unit, integration, robustness).

Mechanical and enclosure

The enclosure is often perceived as a "simple wrapper", but it is a significant cost line. Mechanical engineering must integrate thermal constraints, sealing (IP rating, IEC 60529), ergonomics and manufacturability. The choice between an off-the-shelf enclosure and a custom design changes the budget radically.

Tooling for plastic injection moulding is a heavy upfront investment. You also need to count mechanical prototyping iterations (3D printing, CNC machining) before you freeze the design for production tooling.

Certification (CE, FCC, RED)

No electronic product can be sold in Europe without CE marking, nor in the United States without FCC certification. For radio products (Bluetooth, Wi-Fi, LoRa), the RED directive adds further requirements. CE and RED certification for connected objects involves accredited-lab testing, technical documentation and sometimes several lab passes when the first attempt fails. According to ETSI, the European Telecommunications Standards Institute (etsi.org) and CEPT (cept.org), the harmonised standards EN 301 489 (radio EMC) and EN 300 328 (2.4 GHz ISM band) structure most RED test campaigns.

Certification cost scales with:

• The number of applicable standards (EMC, electrical safety, radio, SAR, etc.).
• The application sector (consumer, medical, automotive; each has its own framework).
• The quality of upstream pre-compliance work.

Summary table: phases and relative effort

The table below compares the relative effort, risks and optimisation levers per phase. It gives decision-makers a synthetic view before they dive into the detailed phase-by-phase discussion.

Phase	Relative effort	Main risk	Optimisation lever
Feasibility study	Low to medium	Poorly qualified needs	Stabilised specification
Schematic + PCB routing	High	Respin from a functional bug	Upstream DFM and DFT reviews
Prototyping EVT/DVT/PVT	Medium to high	Multiple iterations	Right-first-time approach
Firmware / software	Variable (stack-dependent)	Undersized radio/security stack	Proven platform, automated tests
Mechanical / enclosure	Medium (high if custom tooling)	Unamortised injection tooling	Off-the-shelf enclosure when possible
Certification CE/FCC/RED	Medium to high	EMC or RED failure in the lab	Internal pre-compliance
Industrialization (DFM/DFA)	Medium	Series scrap, cost of non-quality	DFM integrated from schematic

Industrialization (DFM / DFA)

Design for Manufacturing (DFM) is the phase where the product is optimised for series production. A design that works in prototype form may turn out to be impossible or too costly to produce at scale. This phase covers PCB adaptation to series-fabrication constraints, component selection driven by long-term availability, and the definition of assembly processes.

A well-run DFM cuts unit production cost. A neglected DFM multiplies scrap, rework and cost of non-quality in series.

The factors that multiply the cost

Cost multipliers are the project parameters that, at equal complexity, weigh heavily on the final budget. We distinguish six families: product complexity, target volume, sectoral regulatory constraints, radio connectivity, finish level and timeline. Identifying these factors at scoping time lets you make informed trade-offs between features, quality, schedule and cost. At AESTECHNO, we have observed that two projects of equivalent complexity can diverge significantly in final budget based purely on sectoral regulation and target volume choices.

Product complexity

This is the most obvious factor and also the hardest to quantify in advance. PCB layer count, presence of high-speed signals, RF module integration and advanced power management all increase engineering time and respin risk.

A single-board product with a microcontroller and a few sensors is in a totally different complexity class from a multi-board system with an application processor, DDR memory, cellular connectivity and a touch-screen interface.

Production volume

Target volume influences development cost as much as unit cost. For a prototype or a small batch, we prioritise speed and flexibility, accepting a higher unit cost. For larger volumes, the industrialization investment (DFM, tooling, test jigs) is amortised over the quantity and reduces unit cost.

The transition from prototype to series is a topic in its own right, covered in our guide on prototype to series industrialization.

Regulatory constraints

A standard consumer product needs only classic CE marking. A medical device falls under IEC 62304 for software and the MDR for placing on the market. Automotive equipment must comply with IATF 16949. An aerospace product follows DO-254 and DO-178C. Each regulated sector adds layers of documentation, testing and validation that significantly increase development cost. According to the IEC, the International Electrotechnical Commission (iec.ch), and according to ISO, the International Organization for Standardization (iso.org), the pair IEC 62368-1 (audio/video/ICT equipment safety) and IEC 60601-1 (medical electrical) governs most safety requirements outside automotive, while the IEC 61000-4-2 to IEC 61000-4-6 families cover industrial EMC tests. On the cybersecurity side, the NIS2 directive and the Cyber Resilience Act (CRA) impose Software Bills of Materials (SBOM, CycloneDX or SPDX) and practices aligned with NIST SP 800-218 for digital products.

Connectivity

Each communication technology adds a layer of technical and regulatory complexity. Bluetooth Low Energy has become relatively accessible thanks to pre-certified modules. Wi-Fi adds power-consumption and certification constraints. LTE or NB-IoT pull in operator certification and recurring connectivity fees. Satellite communication still sits an order of magnitude above in complexity and cost.

Finish level

There is a wide gap between a functional prototype (proof-of-concept) and a finished product ready for sale. The PoC validates a technical concept. The finished product integrates the production enclosure, the certifications, user documentation, packaging and a guaranteed reliability over the product life. This step from PoC to sellable product often represents a large share of the total budget.

Timeline and urgency

A tight schedule has a price. Accelerated PCB fabrication, expedited component sourcing and emergency team mobilisation all generate surcharges. Conversely, a realistic schedule from the start lets you optimise sourcing cost and plan resources efficiently.

The hidden costs nobody mentions

The hidden costs of an electronic development are the line items that surface during the project even though they were not budgeted at scoping time. The most frequent are: PCB respins, certification failures, component shortages, injection-mould tooling, series test fixtures and post-launch software maintenance. Knowing them upfront lets you build realistic provisions and reduce financial risk. In our practice, these hidden line items are the leading source of overruns, well ahead of an initial underestimation of engineering effort.

PCB respins

A respin is a new version of the printed circuit board made necessary by an issue identified during prototyping. Each respin involves schematic and/or routing changes, a new fabrication, a new assembly and new test campaigns. The cost of a respin is not only financial: it is also time lost on the schedule.

The right-first-time approach aims to minimise these iterations by investing more in design review, simulation and validation before fabrication.

Failed certification

A common pattern we observe in our lab: a failure on EMC or radio certification tests forces a partial or complete redesign, followed by another lab campaign. We have measured these round trips as the single largest cost-and-delay event of a project. A solid pre-compliance strategy, using EN 55032 protocol measurements with internal near-field probes, sharply cuts this risk before the accredited lab pass. In our practice, the protocol relies on Tektronix TekExpress pre-scans applied during DVT, well before the 2026 lab booking window.

Component shortages

The electronic component market is subject to shortage cycles that can force a redesign mid-development. A part selected at specification time can become unavailable months later, forcing the team to find an equivalent, modify the schematic and revalidate the design.

Plastic injection tooling

For custom enclosures in injection-moulded plastic, the tooling (the mould) is a heavy upfront investment. This cost is often underestimated, even more so if design changes force tool rework or replacement.

Production tests

Series production needs test means: functional test jigs, in-series firmware programming, integrity testing, calibration. Designing and building those tools is a development cost often forgotten in the initial budget.

Post-launch software maintenance

Once the product hits the market, development does not stop. Bug fixes, security updates, feature evolution and technical support: software maintenance is a recurring cost that must be anticipated from product design.

How to reduce costs without sacrificing quality

Reducing cost without compromising quality consists of activating five precise levers. These levers are: specification stabilisation, right-first-time approach, DFM (Design for Manufacturing) integration from the schematic, internal EMC pre-compliance and reuse of proven platforms. The point is to take the right decisions at the right time, to invest at the key stages to avoid downstream overruns. According to ADEME, the French Agency for Ecological Transition (ademe.fr), eco-design principles applied from the upstream phase reduce the material and energy footprint of the finished product while optimising manufacturing costs.

Define a precise specification from the start

Specification changes mid-project are the leading cause of budget overruns. A complete product specification that defines features, expected performance, environmental constraints and target volumes lets you size the project correctly from the start.

Aim for right-first-time

The right-first-time approach consists of investing more upstream (deep design reviews, simulations, risk analyses) to reduce iteration count downstream. Each respin avoided is a direct saving of time and money. Despite the apparent cost of upfront review hours, we have measured that this approach is the most effective lever to keep the overall budget under control. Contrary to the temptation to ship a "quick first prototype", in our practice the second pass with full-stack EMC pre-checks closes the budget faster than three respin loops.

Integrate DFM from design

Thinking about manufacturability from the design phase, not after prototyping, avoids costly redesigns at industrialization. Integrated DFM optimises component placement, assembly processes and production testability.

Run EMC pre-compliance before the lab

Electromagnetic compatibility tests in an accredited lab are expensive. Performing pre-compliance measurements internally lets you identify and fix issues before the official pass, avoiding failures and costly retests.

Reuse proven platforms

Rather than designing every project from a blank sheet, reusing proven hardware and software bricks (System-on-Module / SOM, standard MCUs such as STM32, ESP32, Nordic nRF52, Raspberry Pi Compute Module with mature ecosystems, well-mastered firmware platforms such as FreeRTOS, Zephyr, Yocto, EDA design tools such as Altium and KiCad) reduces development time and technical risk.

In-house vs outsourced development

The arbitration between an in-house team and an external design house corresponds to a structural choice between fixed costs (salaries, tools, training, social charges) and variable costs (per-project or fixed-price billing). The arbitration depends on expected project volume, skills already in place, time-to-start and intellectual-property handling. According to INSEE, the French national statistics institute (insee.fr), and according to Kompass, a reference B2B directory (kompass.com) and PagesJaunes (pagesjaunes.fr), France hosts several hundred electronic design houses across the territory, with cost structures that vary with location and specialisation. We cover this in our dedicated piece: Make or Buy: when to design in-house vs outsource.

The main comparison points in summary:

• Fixed vs variable costs. An in-house team is a fixed cost (salaries, social charges, tools, training) whether the project generates work or not. A design house turns these costs into variable per-project costs.
• Available skills. A design house gathers complementary skills (hardware, firmware, RF, EMC, certification) that would be costly for an SME to assemble in-house.
• Time-to-start. An external partner can start within days. Building an in-house team takes months of recruitment.
• Intellectual property. In-house gives direct control. With a partner, IP transfer must be contractually written.

To go further, see our guide on outsourcing electronic design. Partner location also significantly shapes the cost structure: our guide on manufacturing in China vs France reviews the real gaps in cost, lead time and risk.

How AESTECHNO keeps the budget under control

Budget control at AESTECHNO consists of articulating four operational pillars. Those pillars are: transparent estimation by phase and deliverable, milestones with explicit acceptance criteria, continuous communication on technical risks, and capitalised experience across projects of varying complexity. We know that for a decision-maker, budget visibility matters as much as the technical quality of the deliverable. Here is how we do it concretely.

Transparent estimation from the study phase

From the first conversation, we break the project down into clearly identified phases and deliverables. Each phase carries its own estimate, which lets you visualise the budget split and prioritise the investments.

Clear milestones with defined deliverables

The development is structured by milestones with precise deliverables and acceptance criteria. This approach gives you visibility on project progress and budget consumption at every step. No tunnel effect.

Continuous communication, no surprise

We keep regular communication going throughout the project. Technical difficulties, identified risks and decisions that affect the budget are shared in real time. A problem identified early always costs less to fix than a problem found late.

Experience across varied complexity

With more than 10 years of experience and projects spanning a wide complexity range, from a simple sensor board to a complete embedded system with connectivity and certification, we have built a reliable estimation capability. Across 65 projects since 2022, we know what is expensive, what is risky, and where to spend effort to optimise the cost-result ratio. We deliver 100% success rate on CE/FCC certifications when the EMC pre-compliance protocol is followed.

Real-world cases: three archetypes of budget drift

The overruns we observe most often, with their root cause and our recommendation. No customer names (NDA), but recurring patterns any product decision-maker will recognise.

• Case 1: certification respin after RED failure. A board passes functionally, fails in the lab on EN 301 489 (radio EMC); the team goes back to routing to rework planes and filters. Contrary to the idea that a "first pass" is economical, the 6 to 12-week respin (PCB plus components plus lab re-booking) wipes out any saving made on initial design. We recommend an internal EMC pre-scan with our Tektronix TekExpress instrumentation before any billed lab campaign.
• Case 2: redesign for component shortage. An MCU goes out of stock without a pin-compatible alternative, forcing schematic, routing and sometimes firmware rework. Contrary to the temptation to wait for an announced restock, the lost product window typically costs more than the redesign. We recommend a SiliconExpert analysis (lifecycle, EOL, NRND) and Octopart screening (multi-source) at BOM scoping, not at the end of the project. In practice we replaced 18 of 20 BOM lines on a recent shortage exposure inside a single sprint.
• Case 3: EMC rework on a product already in series. A batch ships, a firmware change shifts the emitted spectrum, the product drops below compliance. Contrary to the belief that "a certified product stays certified", any significant change re-opens RED conformity. We recommend an EMC change-control procedure from production onwards, with an internal pre-scan before each radio-firmware revision.

Budget estimation tools and standards

Reliable estimation rests on named, structured data sources. According to Octopart and according to Findchips, the aggregated multi-distributor BOM price is available for direct lookup. According to SiliconExpert, the lifecycle data (Not Recommended for New Designs / NRND, End of Life / EOL, RoHS/REACH compliance) lets us filter risky components at scoping. According to Digikey and according to Mouser, the spot stock and distributor lead times shape the sourcing strategy. On the public-funding side, according to Bpifrance, the Crédit Impôt Recherche (CIR) and the innovation loan cover part of eligible development. According to ADEME, eco-design subsidies support projects that limit their material footprint. On the certification side, the cost framework depends directly on the targeted IPC class (Class 1 consumer, Class 2 industrial standard, Class 3 medical/aerospace/military): each class imposes different design rules, tolerances, traceability and tests, and the unit PCB cost can vary by 30 to 200% between Class 2 and Class 3 depending on complexity.

Contrary to the temptation to pick the cheapest possible BOM, the respin penalty (typically 6 to 12 weeks) makes a 10 to 15% more expensive but multi-source BOM almost always profitable at 18 months. Despite a higher headline figure on day one, the avoided respin pays back several times over. Our signature stance, the product design IS the production design, with EMC pre-compliance and IPC integrated from the schematic, is precisely aimed at eliminating the costliest class of overruns: the industrialization respin. Combined with our shortage-mitigation experience (pin-compatible alternatives or focused redesign), this approach stabilises the budget over 18 to 24 months, not only at prototype delivery. We have measured 3 weeks saved on average per project where TekExpress pre-qualification ran before the accredited lab.

Bottom line

• An electronic product development cost is structured across seven phases, and the line items most often underestimated are upstream (specification, feasibility) and downstream (industrialization, post-launch maintenance).
• Sectoral regulation is the single biggest cost multiplier; medical, automotive and aerospace dominate any technological choice.
• Hidden costs (PCB respins, certification failures, component shortages, injection tooling, production test fixtures, software maintenance) drive most overruns. Provision for them at scoping.
• The most effective levers to reduce cost without sacrificing quality are: stabilised specification, right-first-time, integrated DFM, internal EMC pre-compliance and reuse of proven platforms.
• Estimation transparency, with phase-by-phase budgets and contractual milestones, is the most reliable way to avoid the tunnel effect and steer the project budget across 18 to 24 months.

Frequently asked questions

This FAQ groups the most frequent questions on budget estimation and consists of answering directly the points that condition the initial scoping of an electronic product.

How much does it cost to develop an electronic board?

The cost depends on circuit complexity (component count, PCB layers, high-speed interfaces, radio connectivity), prototyping iteration count and required certifications. Each project is unique. We recommend defining a precise specification as the basis for estimation. We refuse to publish absolute figures because real numbers vary too widely with scope.

What are the main cost line items?

The major line items are hardware design (schematic + PCB routing), firmware/software development, prototyping (fabrication and assembly), certification (CE/FCC/RED), mechanical (enclosure) and industrialization (DFM/DFA, tooling, test jigs). The relative weight of each line varies with the type of product.

How long does it take to develop an electronic product?

Typical lead time runs from a few months for a simple product based on mastered technologies, up to over a year for a complex system needing several iterations and sectoral certifications. The schedule depends on technical complexity, component availability and the customer's responsiveness on validations.

How do I avoid budget overruns?

The three most effective levers: a complete and stabilised specification before kickoff, a right-first-time approach that cuts respins, and transparent communication between the customer and the development team. Provisioning for risks (components, certification) is also prudent.

Should I outsource or recruit in-house?

It depends on your project volume, your core business and your time horizon. Outsourcing offers flexibility and immediate access to varied skills. In-house suits companies with a continuous flow of developments. Read our Make or Buy analysis for a complete decision framework.

Does AESTECHNO offer free estimates?

Yes. We offer a first 30-minute exchange to understand your need and provide a phase-by-phase estimate. This exchange is free and non-binding. Contact us at contact@aestechno.com or via our contact form.

Related articles

This selection of related articles is a reading path that lets you dig deeper into the complementary aspects of budget estimation: scoping, DFM, industrialization, certification and outsourcing strategies.

• Make or Buy: design in-house vs outsource
• How to write an electronic product specification
• DFM: Design for Manufacturing in electronics
• From prototype to series: electronic product industrialization
• CE and RED certification for connected IoT objects
• Electronic design house: how to choose the right partner
• More articles on the AESTECHNO blog