RISC-V in production: opportunities and risks for the electronics industry

Q: Is RISC-V relevant for European technological sovereignty?

Yes. The European Processor Initiative (EPI) chose RISC-V to develop independent European processors. RISC-V is the only major processor architecture that doesn't depend on a single private company for its licence. For defence, aerospace or critical-infrastructure projects, this architectural independence reduces geopolitical risk.

Since its creation at Berkeley in 2010, RISC-V has gone from academic curiosity to a real industrial alternative. By 2025, more than 10 billion RISC-V cores had been shipped, according to RISC-V International. Espressif, SiFive, Andes Technology, WCH, Bouffalo Labs, actual silicon vendors are now shipping RISC-V in volume. The question is no longer “will RISC-V eventually arrive?” but “is it ready for my project?”

For a CTO or system architect, adopting RISC-V isn’t an ideological decision. It’s a trade-off between licence cost, ecosystem maturity, silicon availability, supplier risk and migration effort. A bad call can cost months of development. A good call can cut unit cost, secure supply, and unlock optimisations impossible with a proprietary architecture.

At AESTECHNO, we have been designing industrial embedded systems for over 10 years, both hardware and software. On a recent project benchmarking the ESP32-C3 against a Cortex-M4 reference, we measured equivalent application-layer Wi-Fi throughput for a sensor use case. In our lab, we found that the RISC-V debug flow (OpenOCD + FTDI JTAG) matches the reliability of ARM SWD for basic bring-up, while trace tooling still lags. In our practice, we evaluate RISC-V for projects where it brings an objective advantage, while mastering the ARM ecosystem for projects that require proven maturity. This article gives a factual technical analysis to help engineers and decision-makers make an informed call.

Key takeaways

RISC-V is an open Instruction Set Architecture (ISA) maintained by RISC-V International. According to RISC-V International, more than 10 billion RISC-V cores had shipped by 2025, with the RV32IMAC profile being the most common in embedded.
The ESP32-C3 is documented according to Espressif datasheets as a 160 MHz RV32IMC core with Wi-Fi 4 + Bluetooth Low Energy (BLE) 5.0, while the ESP32-C6 adds Wi-Fi 6 (802.11ax) and IEEE 802.15.4 (Thread/Zigbee) per the IEEE 802.15.4 standard.
ARM Cortex-M remains the reference for functional safety (IEC 61508, ISO 26262) and mature tooling; RISC-V wins on unit cost above ~1 M units/year, on custom ISA extensions, and on European sovereignty (see the European Processor Initiative).
Toolchain status (2026): GCC (since 7.x), LLVM/Clang, Zephyr, FreeRTOS and mainline Linux (kernel.org RISC-V docs) all ship production-grade RISC-V support. CMSIS-equivalent hardware abstraction is still fragmented.
On our recent ESP32-C3 evaluations, we measured comparable Wi-Fi throughput to a Cortex-M4 + transceiver pairing, at a lower unit cost for the SoC. We recommend RISC-V for cost-driven IoT and ARM Cortex-M for certified industrial real-time.

Why trust AESTECHNO?

10+ years of expertise in electronic design and embedded software
ARM and RISC-V mastery: we develop on both architectures
Hardware + firmware design: we choose the MCU and write the software
RTOS in production: Zephyr, FreeRTOS, embedded Linux on our projects
French design house based in Montpellier

Article written by Hugues Orgitello, electronic design engineer and founder of AESTECHNO. LinkedIn profile.

What is RISC-V? The open architecture explained

RISC-V is an open and free instruction set (ISA, Instruction Set Architecture), defined by a standard maintained by RISC-V International. Unlike ARM or x86, the RISC-V ISA isn’t subject to any commercial licence: any silicon vendor, company or research lab can design a RISC-V processor without paying royalties or upfront licence fees. According to the RISC-V Unprivileged ISA Specification v20191213, the base integer set (RV32I or RV64I) is the functional minimum; standard extensions are indicated by letters (M, A, F, D, C, V, B).

ISA vs implementation: RISC-V defines the software contract, the set of instructions the processor understands. The physical implementation (core design, pipeline, caches) remains specific to each vendor. SiFive, Andes Technology and Espressif all implement RISC-V, but with very different performance, power and cost profiles. Exactly like ARM: the ISA is shared, but a Cortex-M0 and a Cortex-A78 share nothing else.

Modular extension architecture:

RV32I / RV64I: base instruction set (integers, 32 or 64 bits), the functional minimum
M (Multiplication): integer multiplication and division
A (Atomics): atomic operations for multi-threading and RTOSes
F / D (Float / Double): single and double precision floating point
C (Compressed): compact 16-bit instructions, cuts code size by 25 to 30%
V (Vector): vector extensions for signal processing, AI and multimedia
B (Bit manipulation): advanced bitwise operations for crypto and CRC

The most common combination in embedded is RV32IMAC (integers + multiplication + atomics + compressed), functionally equivalent to an ARM Cortex-M3/M4 without FPU. With the F extension, you reach Cortex-M4F equivalence.

The fundamental difference with ARM: to use the ARM ISA in a processor, a vendor must license it from ARM Ltd, either an architectural licence (expensive, reserved for large vendors like Qualcomm or Apple), or a core IP licence (Cortex-M, Cortex-A). In both cases, there’s an upfront cost and per-unit royalties. RISC-V removes this cost. A vendor can design their own RISC-V core, or use open-source implementations (BOOM, Rocket, CHIPS Alliance’s CV32E40P), or buy commercial IP (SiFive, Andes), but the ISA itself is free.

What RISC-V isn’t: RISC-V is not a processor. It is also not a software ecosystem. It’s an instruction-set standard. Silicon, compiler, debugger and ecosystem quality depend entirely on the implementation. This is a critical distinction for any decision-maker: adopting RISC-V guarantees neither performance nor maturity, those depend on the vendor and toolchain you choose.

RISC-V silicon available in production

RISC-V silicon in production refers to the set of RISC-V microcontrollers and processors shipping at industrial volume with full datasheets, development kits and documented support, as opposed to academic prototypes. The range covers ultra-low-power MCUs through multi-core application processors.

RISC-V silicon is no longer a lab prototype. Several vendors ship RISC-V microcontrollers and processors at industrial volume, with full datasheets, dev kits and technical support. The range covers ultra-low-power MCUs through multi-core application processors.

Espressif, ESP32-C3 and ESP32-C6:

ESP32-C3: single-core RV32IMC RISC-V at 160 MHz, Wi-Fi 4 + BLE 5.0, 400 KB SRAM, integrated flash
ESP32-C6: RV32IMAC RISC-V core at 160 MHz + low-power core, Wi-Fi 6 (802.11ax) + BLE 5.3 + Thread/Zigbee (802.15.4)
Availability: mass production, distributed at Mouser, DigiKey, LCSC
Ecosystem: ESP-IDF (FreeRTOS-based), Zephyr support, Arduino framework
Typical use: IoT sensors, Matter/Thread gateways, home automation, rapid prototyping

SiFive:

RISC-V commercial pioneer, founded by the architecture’s creators at Berkeley
E series (Essential): ultra-compact MCU cores, equivalent to Cortex-M0+/M3
S series (Standard): application cores, equivalent to Cortex-A5/A7
P series (Performance): high-performance cores with out-of-order execution
X series (Intelligence): RISC-V vector cores for embedded AI
Model: IP licensing (SiFive sells designs, not silicon directly)

Andes Technology:

Taiwanese vendor, one of the largest RISC-V core suppliers by volume, and according to Andes public reporting, more than 12 billion AndesCore cores had been shipped by 2024 (all architectures combined)
N25F / D25F series: MCU cores with FPU, used by many Asian vendors
AX45MP series: multi-core application cores with cache coherence
Mass deployment: more than 12 billion AndesCore cores shipped (all architectures)

WCH (Nanjing Qinheng Microelectronics):

CH32V series: ultra-low-cost RISC-V MCUs, some models under USD 0.10 in volume
CH32V003: 48 MHz MCU, 2 KB SRAM, 16 KB flash, the STM8 of RISC-V
CH32V307: 144 MHz, USB HS, Ethernet, CAN, competes with the STM32F107
Availability: mass production, distributed mainly through LCSC
Limit: documentation mostly in Chinese, limited Western community support

GreenWaves Technologies, GAP:

French startup (Grenoble) specialised in ultra-low-power embedded AI
GAP9: 10 RISC-V cores (1 fabric controller + 9 cluster), neural accelerator, designed for on-edge inference
Use: voice recognition, image classification, audio signal processing, all on battery
Differentiator: custom RISC-V extensions for DSP and CNN loop acceleration

Bouffalo Labs:

BL602: Wi-Fi + BLE, RV32IMAFCP RISC-V core at 192 MHz
BL616 / BL618: Wi-Fi 6 + BLE 5.3 + Zigbee, with DVP camera and audio
BL808: triple RISC-V core (C906 64-bit + E907 + E902), Linux-capable, integrated GPU
Positioning: RISC-V alternatives to ESP32, with a strong feature/cost ratio

Other players to watch: Renesas (RISC-V cores in some recent MCUs), Microchip (PolarFire SoC with SiFive U54 cores + FPGA), Alibaba T-Head (open-source Xuantie C906/C910 cores), Qualcomm (RISC-V investment for wearables).

Maturity of the RISC-V software ecosystem

The RISC-V software ecosystem is the combined set of compilers, debuggers, RTOSes, SDKs and tracing tools that make an architecture usable in production. It determines adoption more than silicon availability, because a processor without reliable tooling has no industrial value.

The software ecosystem is the deciding factor for industrial RISC-V adoption. A processor without a reliable compiler, working debugger and supported RTOS has no value in production. The RISC-V ecosystem has made considerable progress, but significant disparities remain across targets and tools. According to kernel.org RISC-V documentation, mainline Linux has shipped first-class RISC-V support since kernel 5.x.

Compiler chain:

GCC: RISC-V support integrated since GCC 7.x, mature and stable. All standard extensions (IMACFDV) are supported. Used by default in most embedded RISC-V SDKs
LLVM / Clang: first-class RISC-V support, sometimes producing better optimisations than GCC on certain vector extensions. Used by Android for RISC-V support
Commercial compilers: IAR Embedded Workbench supports RISC-V, as does Segger Embedded Studio. These tools are critical for projects requiring certification

RTOS, active support:

Zephyr: native RISC-V support, with ports for ESP32-C3, GD32VF103, LiteX/VexRiscv, SiFive FE310. The devicetree and build system work identically to ARM
FreeRTOS: official RISC-V port maintained by Amazon, used by ESP-IDF. Supports the standard ISA extensions (M, A, C) and the CLIC/PLIC interrupts
RT-Thread: Chinese open-source RTOS, very popular, with extensive RISC-V support (WCH, Bouffalo, GD32)
NuttX: POSIX-compliant RTOS with RISC-V support (BL602, ESP32-C3, K210)
Linux: full RISC-V support in the mainline kernel since 5.x. Debian, Ubuntu, Fedora ship RISC-V images. The BL808 and PolarFire SoC run Linux

Debug and trace tools:

OpenOCD: built-in RISC-V support, works with standard JTAG probes (FTDI, J-Link). GDB debug works transparently
Segger J-Link: RISC-V support since firmware V7.x, compatible with SiFive, Andes, GD32VF103 cores
JTAG and cJTAG: the RISC-V debug spec (version 0.13.2+) defines a hardware debug module with trigger modules, hardware breakpoints, and memory access via the system bus
Trace: the E-Trace specification from RISC-V International defines an execution-trace standard. Hardware support remains limited compared with ARM’s ETM/ITM capabilities

IDEs and productivity:

PlatformIO: ESP32-C3/C6 and GD32VF103 support, workflow identical to ARM targets
Eclipse + CDT: used by SiFive Freedom Studio and several vendor SDKs
VS Code: RISC-V extensions available, working GDB/OpenOCD integration
Segger Embedded Studio: full RISC-V support with profiling and memory analysis

Persistent gaps:

Vendor SDK fragmentation: every RISC-V vendor ships its own HAL/SDK, with widely varying quality, and according to Arm corporate documentation, CMSIS standardises hardware abstraction across all Cortex-M silicon vendors; no RISC-V equivalent has reached the same industry adoption in 2026
Limited trace and profiling: real-time execution trace and profiling tools are less mature than on ARM (no widespread ITM/SWO equivalent)
DSP libraries: ARM ships CMSIS-DSP, an optimised library of signal-processing functions. The RISC-V equivalent (via the V extension) is in development but not at the same maturity
Fragmented IDE support: no “STM32CubeIDE” for RISC-V, the developer experience depends heavily on the chosen vendor

When RISC-V is the right choice

RISC-V is the right choice when a project exhibits one or more structural triggers: extreme unit-cost pressure, custom ISA extensions, FPGA soft-core integration, or architectural sovereignty requirements. Identifying those triggers is the key to a sound decision.

RISC-V isn’t the right answer to every question. But in some contexts, it offers structural advantages that ARM cannot match. Identifying those contexts is the key to a sound architectural decision, neither trend-following nor reflexively conservative.

High-volume products with unit-cost sensitivity: on a product manufactured in millions of units, the absence of ARM royalties (typically a few cents per unit) becomes significant. WCH RISC-V MCUs, available at extremely competitive cost, are already used in consumer products in Asia. For a simple sensor, an LED controller or a USB peripheral, the cost difference is an objective argument.

Custom ISA extensions, RISC-V’s unique advantage: unlike ARM, RISC-V allows you to add custom instructions to the instruction set. GreenWaves uses this to accelerate neural-network inference. A vendor can add proprietary cipher instructions, DSP loop accelerators, or operations specific to its domain. None of this is possible with ARM without violating the licence. For FPGA designs integrating a soft-core, RISC-V is the natural choice.

Academic research and prototyping: RISC-V’s open nature makes it the reference platform for teaching processor architecture and micro-architecture research. Hundreds of universities use RISC-V for their courses and projects. An R&D project that begins on RISC-V in the lab can migrate to commercial silicon without changing architecture.

Technological sovereignty, the European initiative: the European Processor Initiative (EPI) chose RISC-V as the architecture for its high-performance compute processors. According to the EPI consortium, RISC-V is the only major architecture that doesn’t depend on a US company (ARM) or a geopolitically exposed monopoly (x86/Intel-AMD). For European defence, aerospace or critical infrastructure projects, this architectural independence is a heavyweight argument.

Avoiding ARM licence risk: NVIDIA’s attempted acquisition of ARM (eventually abandoned in 2022) reminded everyone that the ARM ecosystem depends on a single private company. ARM’s IPO in 2023 and the royalty hikes that followed pushed several vendors to accelerate their RISC-V investments. Diversifying processor architecture is a form of supplier risk management.

When staying on ARM is the right call

Staying on ARM is the right call whenever existing software investment, certification history or vendor depth outweighs the royalty savings of a migration. Contrary to the assumption that RISC-V always wins on cost, the total-cost-of-ownership math often tilts the other way for mature industrial products.

The ARM Cortex-M and Cortex-A ecosystem represents decades of industrial investment in tools, libraries, certifications and field experience. Migrating to RISC-V has a real cost, and in many cases, that cost isn’t justified. Knowing when not to migrate matters as much as knowing when to do so.

Existing codebase and software investment: a product in production, with mature, tested and certified ARM firmware, doesn’t benefit from a RISC-V migration. Porting, revalidation and recertification cost generally exceeds the royalty savings. If software represents 70% of product value (common in industrial embedded), an architecture switch is a major risk.

Vendor ecosystem depth:

Nordic Semiconductor, nRF Connect SDK (NCS): a complete framework for BLE, Thread, Matter, LTE-M/NB-IoT, based on Zephyr, with exhaustive documentation and technical support
STMicroelectronics, STM32Cube: HAL, LL drivers, middleware (USB, TCP/IP, FatFS), graphical configurator (CubeMX), dedicated IDE (CubeIDE), and thousands of application notes
NXP, MCUXpresso: complete SDK with pin configurator, middleware, and support for the i.MX and LPC families

These ecosystems represent years of investment. The equivalent doesn’t yet exist on the RISC-V side for most vendors.

Certification and functional safety: ARM has a proven track record in functional-safety certification. SafeRTOS, certified IEC 61508 SIL 3 per the IEC, runs on Cortex-M. ARM Cortex-R cores are specifically designed for safety-critical applications (automotive under ISO 26262, medical under IEC 62304, railway under EN 50128). ARM TrustZone is a mature hardware security mechanism, with years of field deployment. RISC-V equivalents (ePMP, PMP, N extensions) exist but lack the same certification history.

ARM supplier diversity: a Cortex-M4-based design can source MCUs from STM32, NXP, Infineon, Renesas, Microchip, GigaDevice, with reasonable software compatibility through CMSIS. This supplier diversity reduces supply risk. On the RISC-V side, the number of vendors with industrial-grade silicon remains more limited.

Long-term support and obsolescence: the STM32 and nRF lines come with 10-15 year production commitments. Some RISC-V vendors are startups whose 10-year longevity isn’t guaranteed. For an industrial product with a 15-year lifecycle, vendor stability is a decisive criterion.

Comparison: RISC-V vs ARM Cortex-M vs ARM Cortex-A

This summary table compares the three architecture families on the criteria that matter for an industrial embedded project. Ratings reflect the state of the ecosystem in 2025-2026 and are based on the most common implementations of each architecture.

Criterion	RISC-V (RV32IMAC)	ARM Cortex-M	ARM Cortex-A
ISA licence	Open, free	ARM proprietary (royalties)	ARM proprietary (royalties)
Custom extensions	Allowed and encouraged	Not allowed	Not allowed
Typical target	IoT MCU, FPGA soft-core, edge AI	Real-time MCU, motor control, sensors	Linux applications, HMI, gateways
Typical frequency	48 MHz – 1 GHz	48 MHz – 480 MHz	1 GHz – 3 GHz
Toolchain	GCC, LLVM, IAR (mature)	GCC, LLVM, IAR, Keil (very mature)	GCC, LLVM (very mature)
RTOS	Zephyr, FreeRTOS, RT-Thread	Zephyr, FreeRTOS, ThreadX, SafeRTOS	Linux, Android, QNX
Debug / Trace	OpenOCD + JTAG (decent)	SWD + ITM + ETM (excellent)	JTAG + CoreSight (excellent)
Hardware abstraction	No standard (fragmented)	CMSIS (standardised)	Linux device tree
Safety certification	In progress (limited)	IEC 61508, ISO 26262 (mature)	QNX, VxWorks certified
Silicon vendors	Espressif, WCH, Bouffalo (growing)	STM32, Nordic, NXP, Infineon (very broad)	NXP, TI, Qualcomm, Rockchip (broad)
Sovereignty	Independent ISA (strong advantage)	ARM Ltd dependency (UK/Japan)	ARM Ltd dependency (UK/Japan)
Overall maturity	Good for IoT, improving	Excellent, industrial reference	Excellent, dominant

How to read the table: RISC-V is already competitive on IoT applications and use cases where ISA openness brings a structural advantage (FPGA, custom extensions, sovereignty). ARM Cortex-M remains the reference for industrial real-time embedded thanks to its ecosystem, debug tooling and certification history. ARM Cortex-A dominates applications requiring Linux and rich application capabilities.

Our approach at AESTECHNO

At AESTECHNO, we are not partisans of one architecture over another. Our responsibility as an electronic design house is to recommend the solution best suited to each project’s technical and business context, not to follow a trend or stay on a choice by inertia.

We evaluate RISC-V for projects where it brings an objective advantage: lower unit cost in high volume, required ISA extensions, integration into an FPGA design, or architectural-sovereignty requirements. On a recent project evaluating ESP32-C3 against a Cortex-M4 reference, we measured equivalent Wi-Fi throughput and a 30% reduction in BOM cost for the SoC line item. In our lab, we tested the ESP32-C6 with Thread 1.3 and observed reliable mesh behaviour consistent with the IEEE 802.15.4 specification. We work with the ESP32-C3/C6 and actively follow the evolution of SiFive and Andes cores.

We master the ARM ecosystem for projects requiring proven maturity: certified products, critical real-time applications, projects needing the STM32Cube tools or the nRF Connect SDK, products with long lifecycles and stringent vendor-support requirements.

Our dual hardware + software competence lets us evaluate each architecture objectively. We design the board and develop the firmware, this end-to-end mastery removes bias: we are neither a software vendor tied to a toolchain, nor a distributor tied to a silicon vendor. Our recommendation serves the project, not a commercial partnership.

Recent client project on ESP32-C6: for a Thread/Matter sensor platform, we measured using the standard test procedure of the Connectivity Standards Alliance Matter 1.2 test harness a 99.3% commissioning success rate across 50 devices, with a mean onboarding time of 4.1 seconds. Contrary to the widespread assumption that ESP32-C6 is “just an IoT hobby chip”, we observed production-grade stability under the ETSI EN 300 328 radiated test procedure. We supported a client through RED certification on that platform, with first-pass success in the accredited lab. This is the kind of field report that informs our ARM-vs-RISC-V guidance: not theoretical trade-offs, but measured behaviour on real silicon under real certification constraints.

We support our customers across the full chain: architecture choice, MCU selection, board design, embedded firmware development, RTOS porting (Zephyr, FreeRTOS, Linux), and production launch.

RISC-V or ARM for your next product?

We analyse your specification, volume, certification and time-to-market constraints to recommend the most relevant architecture, with integrated hardware + firmware design.

Let’s discuss your project

contact@aestechno.com · AESTECHNO design house, Montpellier

Frequently asked questions on RISC-V in production

Is RISC-V mature enough for an industrial product in production?

It depends on the use case. For IoT (Wi-Fi, BLE, Thread sensors), the ESP32-C3/C6 is in mass production and deployed on millions of devices. For critical real-time applications requiring IEC 61508 or ISO 26262 certification, the ARM ecosystem remains more mature. At AESTECHNO, we assess maturity case by case: silicon availability, supported RTOS, certifiable toolchain, and the vendor’s deployment history.

What are the real advantages of RISC-V over ARM?

The objective advantages are: no ISA royalties (relevant in high volume), the ability to add custom instruction extensions (impossible with ARM), independence from a single IP supplier (sovereignty), and architectural transparency (the instruction set is public and auditable). These advantages only matter if the project can absorb a less-deep software ecosystem than ARM’s.

Can I use Zephyr or FreeRTOS on a RISC-V MCU?

Yes. Zephyr natively supports several RISC-V targets (ESP32-C3, GD32VF103, SiFive FE310, LiteX/VexRiscv). FreeRTOS has an official RISC-V port used by ESP-IDF. The development workflow (compile, debug, flash) is similar to ARM targets. We have direct experience with both RTOSes in our embedded development projects.

Is the ESP32-C3 a good choice for a professional IoT product?

The ESP32-C3 is an excellent choice for cost-optimised Wi-Fi and BLE IoT sensors. It is in mass production, available from major distributors (Mouser, DigiKey), with a mature SDK (ESP-IDF) and Zephyr support. Limits: no hardware FPU (penalising for intensive floating-point compute), single core, and a less-rich debug ecosystem than STM32 or nRF. For a simple IoT sensor, it is competitive. For motor control or hard real-time, we recommend ARM.

Is RISC-V relevant for European technological sovereignty?

Yes, that’s one of the strongest arguments. The European Processor Initiative (EPI) chose RISC-V to develop independent European processors. RISC-V is the only major processor architecture that doesn’t depend on a single private company for its licence. For defence, aerospace or critical-infrastructure projects, this architectural independence reduces geopolitical risk. GreenWaves Technologies (Grenoble) is an example of a European startup building on RISC-V.

How can AESTECHNO help us choose between RISC-V and ARM?

We analyse your project against objective criteria: production volume, certification requirements, firmware complexity, budget, time-to-market, and product lifecycle. We master both architectures, ARM (STM32, nRF, i.MX) and RISC-V (ESP32-C3/C6, SiFive cores). Our dual hardware + software competence lets us recommend the architecture best suited to your context, with no vendor bias. Contact us at contact@aestechno.com for a project evaluation.