RISC-V in 2026: 25% Market Share, RVA23, and the x86 / ARM Showdown

According to multiple sector analyses published in early 2026, RISC-V crosses the 25% global market share threshold, distributed across application processors, microcontrollers and AI accelerators. For the first time in twenty-five years, the x86 / ARM duopoly officially becomes a trio. The trajectory is not an accident: it builds on the ratification of the RVA23 profile by RISC-V International, on the arrival of high-end cores designed by Jim Keller at Tenstorrent, on Canonical's claim that 2026 is the year of Linux on the RISC-V desktop, and on automotive (Infineon) and Chinese (Xiangshan, Ruyi OS) adoption that turns the open ISA into a piece of national infrastructure.

At AESTECHNO, an electronics design house based in Montpellier, France, we have followed the RISC-V ecosystem since its early industrial releases. We have evaluated it on multiple comparative studies in 2025 and 2026, supported clients on RISC-V SoC qualification for IoT and industrial platforms, and we keep seeing the same question come back at every platform refresh: "should we switch?". This article covers what really changed in 2026, what to watch at Computex (June 2 to 5, 2026), and how to call the decision for your next platform.

The 25% threshold: why 2026 is different

The 25% market share figure announced in early 2026 is not a single linear number: it aggregates application CPUs (still a minority for RISC-V), microcontrollers (where RISC-V has already replaced ARM Cortex-M on several ranges), and dedicated AI accelerators (the segment where free RTL saves months and licensing budgets). It is that aggregation, across three different markets with different dynamics, that produces the crossing.

The analysis published by RISC-V International and echoed by several sector houses positions RISC-V as the "third pillar" of computing, alongside x86 (still dominant on Intel and AMD servers) and ARM (which holds mobile and high-end embedded). The segment where the swing is fastest is industrial embedded and IoT: the royalty-free promise combined with open RTL changes the cost / supply-chain risk equation.

At AESTECHNO, on our last three industrial IoT sensor projects, we systematically included RISC-V in the pre-study phase, even when the client arrived with an ARM preference. The discussion that comes out is no longer "is RISC-V ready?" but "which is your preferred RISC-V vendor, and what does the ten-year TCO look like?".

RVA23: the spec that changed the industry

RVA23 is a RISC-V platform profile ratified by RISC-V International in October 2023 that standardises the mandatory hardware extensions (vectors, hypervisor, scalar cryptography, MMU) a compliant SoC must implement. It makes RISC-V interoperable at distro scale: an Ubuntu RISC-V signed for RVA23 boots on every RVA23 SoC, with no recompilation or per-model kernel rebuild.

The difference with RVA22 (the prior profile) is structural. RVA22 set the bare minimum to run application code. RVA23 adds the vector (V), mandatory for AI and DSP workloads, the hypervisor (H), mandatory for virtualisation and VMs, the scalar cryptography (Zk*), mandatory for performant TLS and secure boot, and several MMU extensions (Svinval, Svnapot) that make context switches fast. This is exactly the minimum a modern Linux distribution needs to consider RISC-V a serious target.

Our reading: RVA23 is the version that makes RISC-V "boring" enough to ship at scale. Before, every RISC-V SoC was a special case the distros had to compile separately. After RVA23, you build once and deploy everywhere. The relevant analogy is the move from ARMv7 to ARMv8: not the most exciting spec to read, but the one that triggers industrial adoption.

AI on RISC-V: the Vector-Matrix Extension (VME)

The Vector-Matrix Extension (VME) is a RISC-V extension being finalised in 2026 that adds native matrix operations, notably outer-products, to the vector instruction set. It enables AI inference on ASIC or MCU at performance-per-watt comparable to the proprietary Apple AMX and ARM SME extensions, while staying royalty-free.

The stake is concrete for edge AI. Today, deploying an image-classification model on an ARM Cortex-M55 MCU goes through CMSIS-NN, which calls the Helium extension (M-Profile Vector Extension, ARM proprietary). The same deployment on a current RISC-V MCU goes through SIMD vector kernels (RVV 1.0), efficient but without native outer-products. VME aligns RISC-V RTL with the matrix-instruction class that modern AI frameworks (TFLite Micro, ONNX Runtime, PyTorch Edge) expect.

For SoC vendors, the calculation is appealing: VME packages an NPU at the ISA level rather than as a third-party accelerator on a side bus. That simplifies the compiler (the LLVM RISC-V backend handles the extension natively), reduces the cybersecurity attack surface (a single instruction space to audit), and shrinks silicon footprint vs a separate NPU. On our comparative studies, this is the extension that makes RISC-V credible for embedded-inference IoT sensors targeting multi-year battery deployments.

Tenstorrent and Ascalon-X: Jim Keller signs the high end

Tenstorrent, led by Jim Keller, is preparing the Ascalon-X core family to take on ARM Neoverse V3 in the high-performance server segment. To recap: Jim Keller is the architect behind AMD K8 / K12 / Zen, Apple A4 / A5, Tesla FSD and Intel Xe. When he picks an ISA for his next eight years, the market pays attention.

Ascalon-X is announced as out-of-order, wide superscalar, with focus on memory bandwidth (DDR5, HBM) and integration of proprietary Tenstorrent Tensix NPUs as chiplets. The positioning is clear: compete with ARM Neoverse N3 / V3 and AMD EPYC on cloud servers, not on smartphones. Tenstorrent has also released several smaller cores (Ascalon, Bamboo) under the Apache 2.0 licence as open source, which changes the playing field for design houses that want a serious RISC-V core without negotiating a proprietary licence.

For AESTECHNO, Tenstorrent's arrival in the ecosystem changes two things. First, it gives credibility to high-end RISC-V cores in front of clients who still suspected the open ISA of being limited to embedded MCU. Second, the released RTL gives access to production-ready cores for specialised projects without going through ARM Cortex-A licence negotiation. On a recent AI ASIC industrialisation engagement, the choice came down to ARM Cortex-A78AE licence vs a Tenstorrent RISC-V core: the deciding criterion was the ten-year roadmap, not the upfront licence cost.

Automotive: Infineon commits to RISC-V for the next generation

Automotive is the segment where RISC-V picks up share fastest in 2026. Infineon announced in 2025 its commitment to port the next vehicle MCU generation (successors to the AURIX TC4 family) onto ISO 26262 ASIL-D-certified RISC-V cores. Bosch, NXP, and several Chinese tier-1s follow. The motivation: control the silicon roadmap of the software-defined vehicle (SDV) without depending on a vertical ARM roadmap.

The automotive segment imposes constraints other markets do not have: real-time determinism, ISO 26262 traceability from RTL to runtime, fifteen-year support windows. RISC-V gets there thanks to the maturation of the certification ecosystem: ISO 26262 ASIL-D RISC-V cores now exist at Andes, SiFive, Codasip, and several Chinese houses. The European Cyber Resilience Act, applicable from end of 2027, adds an additional argument in favour of an auditable open-source supply chain.

Our observation at AESTECHNO: for automotive and off-highway clients we cross paths with on sensor and gateway projects, the RISC-V conversation moved in 2025-2026 from research to RFP. The challenge for European design houses is to have credible RISC-V automotive references on the shelf, today.

The Chinese path: Xiangshan, Ruyi OS, and sovereignty

The Beijing Open Source Chip Research Institute (BOSC) develops Xiangshan, a fully open-source high-performance RISC-V core. The current generation (third generation, codename Kunminghu) reaches performance levels that put RISC-V in the same league as recent server-class Cortex-A. The RTL is under permissive licence, the netlist is taped out by Chinese fabs, and the project includes the world's first open-source network-on-chip IP.

In parallel, Ruyi OS became the first native RISC-V Linux operating system to support the RVA23 profile out of the box. For China, RISC-V is not just a licensing question: it is digital-sovereignty infrastructure facing US ARM restrictions and tariffs on Western SoCs. This dynamic is creating a parallel RISC-V ecosystem with its own distros, its own RTL, and its own packaging conventions.

For a European design house, the reading is nuanced. On one hand, the dual offer (Western + Chinese) reinforces the long-term viability of the ISA. On the other, it introduces supply-chain trade-offs (export controls, tariffs, data compliance) that European industrial clients will have to spell out case by case, in connection with the Cyber Resilience Act and upcoming EU directives on digital sovereignty.

Consumer hardware: Framework, Amazfit, Ubuntu desktop

2026 marks the arrival of RISC-V in credible consumer products. Framework Computer welcomed the DC-ROMA Mainboard II on its platform, designed by DeepComputing: ESWIN EIC7702X SoC, SiFive P550 cores, 50 TOPS NPU for local inference. As far as we know, this is the first RISC-V laptop usable daily (compilation, browsing, video) without major compromise.

On the wearable side, Andes Technology powers the Amazfit T-Rex 3 Pro with its AndesCore D25F core. Over one million units shipped, which puts RISC-V firmly into the "shipping at volume" category on the smartwatch segment, long held by ARM Cortex-M and MIPS.

And Canonical declared 2026 the year of Linux desktop on RISC-V, a deliberately bold claim, but a substantiated one: Ubuntu 26.04 LTS RISC-V is available with official support, RVA23 images boot on Framework, on Pine64 Star64, and on the Hifive development boards. Snap package availability and toolchain support out of the box are roughly equivalent to x86 and ARM. For systems developers, this is the first time a RISC-V machine becomes a credible primary work environment.

RISC-V vs ARM vs x86: the 2026 decision matrix

The table below summarises the trade-offs we keep seeing when a client asks "RISC-V, ARM, or x86 for my next platform?". It does not replace a dedicated comparative study, but it sets the scene.

Criterion	RISC-V	ARM	x86
ISA licence model	Royalty-free, RTL often free	Per-seat licence + royalties	Proprietary (Intel / AMD)
Distro ecosystem maturity	RVA23 mature early 2026	Very mature (>15 years)	Historical reference
Native AI / matrix	VME being finalised	SME (ARM proprietary)	AMX (Intel proprietary)
Automotive ASIL-D	Available (Infineon, Andes, SiFive)	Very mature (Cortex-R52, R82)	Off-target
High-end server	Tenstorrent Ascalon-X (incoming)	Neoverse V3 (already shipping)	EPYC Zen 5 / Xeon Granite Rapids
Microcontrollers	Very credible (GD32, ESP32-C, Andes)	Reference (Cortex-M)	Off-target
EU sovereignty	Strong (open European RTL feasible)	Medium (UK / US dependent)	US dependent
10-year silicon TCO	Edge on low-to-medium volumes	Edge on high volumes	Reserved for heavy compute

Computex 2026 (June 2 to 5): what to watch

Computex Taipei runs from June 2 to 5, 2026, on the theme "AI Together". This is the show where the hardware industry announces its cards for the next twelve months. For RISC-V, several announcements are expected:

• SiFive: next-gen P-series cores (P870 or successor), focus on performance per watt and NPU integration.
• Andes Technology: middle-range AndesCore extension and first VME-ready core demos.
• NVIDIA: confirmation or denial of RISC-V usage for the internal microcontrollers of upcoming GPUs (persistent 2024-2025 rumours).
• Tenstorrent: Ascalon-X roadmap and possible additional RTL open-sourcing.
• ESWIN, StarFive, Telink, GigaDevice: RISC-V SoCs for smartphone (StarFive JH7110 successor), TV (ESWIN W8), wearables (Telink), and industrial MCU (GigaDevice GD32V).
• Distros: Canonical, Red Hat, SUSE expected to detail their RISC-V production support.

Our advice for design houses and integrators: if a platform review is scheduled for Q3 2026 or Q4 2026, waiting for Computex output before locking the SoC is rational. The roadmap deltas announced in Taipei in 2026 are significant enough that a choice locked three months before Computex risks being obsolete by time-to-market.

FAQ

Is RISC-V really royalty-free?

The RISC-V instruction set is specified under a free licence by RISC-V International, with no royalties or per-seat licences. Concrete RTL implementations (the cores) are sold under various licences: some are open source (Rocket Chip, BOOM, Ascalon Apache 2.0), others are commercial products (SiFive Performance series, Andes AndesCore, Codasip Bk). The royalty-free model covers the ISA, not necessarily the silicon you integrate.

Can RISC-V replace ARM in smartphones?

Not before 2027-2028 in the high end. The Android software stack (HAL, modems, GPU drivers, Widevine DRM) is currently ARM-centric, and the transition would require a coordinated Google + OEM effort. On feature phones, smartwatches and IoT wearables, RISC-V is already a reality (Amazfit T-Rex 3 Pro, Telink). The smartphone segment where the swing arrives first is Chinese mid-range, without Play Store constraints.

What is RVA23 and why does it matter?

RVA23 is a RISC-V platform profile that standardises the mandatory hardware extensions to run Linux and FreeBSD at distro scale. It makes RISC-V SoCs interoperable: an RVA23-signed kernel boots on every RVA23-compliant SoC, with no rebuild. Before RVA23, every SoC was a special case. After, the industry can ship. This is the equivalent of what ARMv8 was for ARM in 2011: the version that triggers industrial adoption.

Is RISC-V ready for production industrial projects?

Yes for MCU, IoT sensors, edge AI accelerators, and automotive ASIL-D (certified cores available at Andes, SiFive, Codasip, Infineon). More cautious for high-performance cloud servers where ARM Neoverse and AMD EPYC remain references until Ascalon-X actually ships. RISC-V is a defensible choice for any project finalising after Q3 2026, on a family with a published five-year roadmap.

What toolchain and IDE for RISC-V development?

GCC RISC-V and LLVM RISC-V are mature (RVA23 and vector v1.0 supported in both). Professional IDEs (SEGGER Embedded Studio, IAR, Eclipse CDT, VS Code with PlatformIO) support RISC-V since 2023. Zephyr and FreeRTOS have stable ports. For debugging, OpenOCD covers the main probes (J-Link, FT2232, dedicated RISC-V debuggers). It is now a mature professional development environment, not a research project.

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