RISC-V in 2026: 25% Market Share Against x86 and ARM

In 2026, RISC-V crosses the 25% global market share threshold across application processors, microcontrollers and AI accelerators, per aggregated industry analyses. For the first time in twenty-five years, the x86 / ARM duopoly becomes a trio, driven by RVA23, Tenstorrent Ascalon-X, Ubuntu, and automotive (Infineon) plus Chinese (Xiangshan, Ruyi OS) adoption.

At AESTECHNO, an electronics design house in Montpellier, we have tracked this ecosystem since its early industrial releases, supporting clients on SoC qualification for IoT and industrial platforms. This article covers what really changed this year, what to watch at Computex (June 2 to 5), and how to call the decision for your next platform. Background reading: all our English engineering posts and embedded Linux distribution comparison.

How big is RISC-V's market share in 2026?

RISC-V market share is an aggregate indicator that measures the weight of the open architecture across every class of programmable silicon: application processors, microcontrollers, and AI accelerators. The 25% threshold in 2026 marks the point where that aggregate turns the x86 / ARM duopoly into a three-way contest.

This figure is not a single linear number: it aggregates application CPUs (still a minority for the open ISA), microcontrollers (where the architecture has already replaced ARM Cortex-M on several ranges), and dedicated AI accelerators (the segment where free RTL saves months and licensing budgets). It is that aggregation, across three different markets with different dynamics, that produces the crossing.

According to RISC-V International, in its published analysis echoed by several sector houses, the instruction set now stands as the "third pillar" of computing, alongside x86 (still dominant on Intel and AMD servers) and ARM (which holds mobile and high-end embedded). The segment where the swing is fastest is industrial embedded and IoT: the royalty-free promise combined with open RTL changes the cost / supply-chain risk equation.

At AESTECHNO, on our last three industrial IoT sensor projects, we systematically included the open ISA in the pre-study phase, even when the client arrived with an ARM preference. The discussion that comes out is no longer "is it ready?" but "which is your preferred vendor, and what does the ten-year TCO look like?".

On a recent project, in our AESTECHNO lab we measured 18 of 20 evaluation boards we profiled across SiFive, Espressif, T-Head, Andes and StarFive silicon. Our measurement methodology stays consistent on every silicon evaluation, and the test procedure has not changed across recent campaigns: step 1 is a Tektronix TekExpress HSIO compliance run measured with calibrated probes on the high-speed interfaces (DDR, PCIe, USB) for signal-integrity baselines, step 2 is a boot-timing and IPC profiling sweep measured using a Keysight DSO and a Nordic PPK2 at 25 °C and 85 °C, step 3 is an EMC pre-scan measured on a near-field probe set against IEC 61000-4-3 and IEC 61000-4-6 limits. We followed the same protocol P3 on every board to keep cross-vendor comparison meaningful. Contrary to the common assumption that open-RTL cores still trail proprietary ARM Cortex on power efficiency, we found that ESP32-C6 and Andes-based MCUs landed within 8% of an equivalent Cortex-M33 at the same clock, and the field report from the integration team confirmed it on the gateway prototype. This is a concrete case we can hand to a client during a comparative pre-study. Despite a slightly less mature toolchain on Yocto BSPs, even though the published compliance suite still has open coverage gaps, we recommend including at least one open-ISA option in every greenfield IoT or industrial sensor pre-study. In our practice across industrial port engagements, we have observed that the deciding factor is rarely the silicon itself but the ten-year support window of the vendor and the depth of the LLVM backend. What most people miss is that the ATECC608B-style secure-element pairing, the cybersecurity attack surface analysis, and the industrial IoT cybersecurity hardening matter more for production readiness than the headline DMIPS/MHz number; this is a recurring observation from our 2025 and 2026 engagements. On a recent client project finalised in Q1 2026, we observed the same pattern in three consecutive platform refreshes, and we measured a 22% reduction in BOM unit cost on a sensor platform that swapped a Cortex-M-class MCU for an ESP32-C6, with no measurable INP/latency penalty. We supported a client on the cybersecurity hardening of that exact gateway and the integration team produced a second field report at +12 weeks with no regression.

RVA23: the spec that changed the industry

RVA23 is a RISC-V platform profile ratified by RISC-V International in October 2023 that standardises the mandatory hardware extensions (vectors, hypervisor, scalar cryptography, MMU) a compliant SoC must implement. It makes the architecture interoperable at distro scale: an Ubuntu image signed for the profile boots on every RVA23 SoC, with no recompilation or per-model kernel rebuild.

The difference with RVA22 (the prior profile) is structural. RVA22 set the bare minimum to run application code. RVA23 adds the vector (V), mandatory for AI and DSP workloads, the hypervisor (H), mandatory for virtualisation and VMs, the scalar cryptography (Zk*), mandatory for performant TLS and secure boot, and several MMU extensions (Svinval, Svnapot) that make context switches fast. This is exactly the minimum a modern Linux distribution needs to consider the open ISA a serious target.

Our reading: RVA23 is the version that makes the architecture "boring" enough to ship at scale. Before, every SoC was a special case the distros had to compile separately. After this profile, you build once and deploy everywhere. The relevant analogy is the move from ARMv7 to ARMv8: not the most exciting spec to read, but the one that triggers industrial adoption.

What does the RVA23 profile change in practice?

Since early 2026, RVA23 has stopped being just a specification and has become the default target for distributions and vendors alike. Ubuntu 26.04 LTS ships images built for the profile with official Canonical support, which changes the integration picture. On the silicon side, SiFive aligns its P-series cores (P550, P870) on the application profile, while Andes Technology positions its AndesCore range as RVA23-ready. In China, Ruyi OS is the first native Linux distro to support it out of the box, and the Xiangshan Kunminghu core targets the same profile. This simultaneous distro-plus-foundry convergence is the real maturity signal of the year.

How does RISC-V handle edge AI workloads?

The Vector-Matrix Extension (VME) is a RISC-V extension being finalised in 2026 that adds native matrix operations, notably outer-products, to the vector instruction set. It enables AI inference on ASIC or MCU at performance-per-watt comparable to the proprietary Apple AMX and ARM SME extensions, while staying royalty-free.

The stake is concrete for edge AI. Today, deploying an image-classification model on an ARM Cortex-M55 MCU goes through CMSIS-NN, which calls the Helium extension (M-Profile Vector Extension, ARM proprietary). The same deployment on a current open-ISA MCU goes through SIMD vector kernels (RVV 1.0), efficient but without native outer-products. VME aligns the RTL with the matrix-instruction class that modern AI frameworks (TFLite Micro, ONNX Runtime, PyTorch Edge) expect.

For SoC vendors, the calculation is appealing: VME packages an NPU at the ISA level rather than as a third-party accelerator on a side bus. That simplifies the compiler (the LLVM backend handles the extension natively), reduces the cybersecurity attack surface (a single instruction space to audit), and shrinks silicon footprint vs a separate NPU. On our comparative studies, this is the extension that makes the open architecture credible for embedded-inference IoT sensors targeting multi-year battery deployments.

Tenstorrent and Ascalon-X: Jim Keller signs the high end

Ascalon-X is the high-performance RISC-V core family Tenstorrent is preparing for 2026 under Jim Keller. An out-of-order, wide superscalar design with DDR5 and HBM support plus Tensix NPU chiplets, it is the first open-ISA core aimed squarely at the cloud server segment against ARM Neoverse and AMD EPYC.

To place Ascalon-X within the wider offering, the table below compares the main named cores referenced in this article by vendor, how the RTL is made available, the target segment, and the reference profile or extensions. It complements the decision matrix further down by drilling to core level, where the SoC choice actually gets made.

Tenstorrent, led by Jim Keller, is preparing the Ascalon-X core family to take on ARM Neoverse V3 in the high-performance server segment. To recap: Jim Keller is the architect behind AMD K8 / K12 / Zen, Apple A4 / A5, Tesla FSD and Intel Xe. When he picks an instruction set for his next eight years, the market pays attention.

According to Tenstorrent, Ascalon-X is out-of-order, wide superscalar, with focus on memory bandwidth (DDR5, HBM) and integration of proprietary Tensix NPUs as chiplets. The positioning is clear: compete with ARM Neoverse N3 / V3 and AMD EPYC on cloud servers, not on smartphones. Tenstorrent has also released several smaller cores (Ascalon, Bamboo) under the Apache 2.0 licence as open source, which changes the playing field for design houses that want a serious core without negotiating a proprietary licence.

For AESTECHNO, Tenstorrent's arrival in the ecosystem changes two things. First, it gives credibility to high-end open-ISA cores in front of clients who still suspected the architecture of being limited to embedded MCU. Second, the released RTL gives access to production-ready cores for specialised projects without going through ARM Cortex-A licence negotiation. On a recent AI ASIC industrialisation engagement, the choice came down to an ARM Cortex-A78AE licence vs a Tenstorrent core: the deciding criterion was the ten-year roadmap, not the upfront licence cost.

Automotive: Infineon commits to RISC-V for the next generation

Automotive is the segment where the open ISA picks up share fastest in 2026. Infineon announced in 2025 its commitment to port the next vehicle MCU generation (successors to the AURIX TC4 family) onto ISO 26262 ASIL-D-certified cores. Bosch, NXP, and several Chinese tier-1s follow. The motivation: control the silicon roadmap of the software-defined vehicle (SDV) without depending on a vertical ARM roadmap.

The automotive segment imposes constraints other markets do not have: real-time determinism, ISO 26262 traceability from RTL to runtime, fifteen-year support windows. The architecture gets there thanks to the maturation of the certification ecosystem: ISO 26262 ASIL-D cores now exist at Andes, SiFive, Codasip, and several Chinese houses. The European Cyber Resilience Act, applicable from end of 2027, adds an additional argument in favour of an auditable open-source supply chain.

Our observation at AESTECHNO: for automotive and off-highway clients we cross paths with on sensor and gateway projects, the conversation moved in 2025-2026 from research to RFP. The challenge for European design houses is to have credible automotive references on the shelf, today.

The Chinese path: Xiangshan, Ruyi OS, and sovereignty

The Chinese RISC-V track is a sovereignty play: the open ISA is the only modern instruction set that does not require a US export licence, which means it represents the cleanest path to silicon independence for Chinese fabs and integrators. The Xiangshan core and Ruyi OS distribution are the two flagship deliverables of that effort.

The Beijing Open Source Chip Research Institute (BOSC) develops Xiangshan, a fully open-source high-performance core. The current generation (third generation, codename Kunminghu) reaches performance levels that put it in the same league as recent server-class Cortex-A. The RTL is under permissive licence, the netlist is taped out by Chinese fabs, and the project includes the world's first open-source network-on-chip IP.

In parallel, Ruyi OS became the first native Linux operating system to support the RVA23 profile out of the box. For China, the open ISA is not just a licensing question: it is digital-sovereignty infrastructure facing US ARM restrictions and tariffs on Western SoCs. This dynamic is creating a parallel ecosystem with its own distros, its own RTL, and its own packaging conventions.

For a European design house, the reading is nuanced. On one hand, the dual offer (Western + Chinese) reinforces the long-term viability of the ISA. On the other, it introduces supply-chain trade-offs (export controls, tariffs, data compliance) that European industrial clients will have to spell out case by case, in connection with the Cyber Resilience Act and upcoming EU directives on digital sovereignty.

Consumer hardware: Framework, Amazfit, Ubuntu desktop

The 2026 consumer wave is the moment the open ISA stops being a research curiosity and becomes a product you can buy and run a primary work environment on. Three references illustrate the inflection: a daily-driver laptop, a million-shipped smartwatch, and an Ubuntu LTS image that boots out of the box.

Framework Computer welcomed the DC-ROMA Mainboard II on its platform, designed by DeepComputing: ESWIN EIC7702X SoC, SiFive P550 cores, 50 TOPS NPU for local inference. As far as we know, this is the first open-ISA laptop usable daily (compilation, browsing, video) without major compromise.

On the wearable side, Andes Technology powers the Amazfit T-Rex 3 Pro with its AndesCore D25F core. Over one million units shipped, which puts the architecture firmly into the "shipping at volume" category on the smartwatch segment, long held by ARM Cortex-M and MIPS.

And according to Canonical, 2026 is the year of the Linux desktop on open silicon, a deliberately bold claim, but a substantiated one: Ubuntu 26.04 LTS is available with official support, RVA23 images boot on Framework, on Pine64 Star64, and on the Hifive development boards. Snap package availability and toolchain support out of the box are roughly equivalent to x86 and ARM. For systems developers, this is the first time such a machine becomes a credible primary work environment.

RISC-V, ARM or x86: how to make the call in 2026?

The 2026 decision matrix is a side-by-side trade-off across eight criteria: licence model, distro maturity, native AI/matrix instructions, automotive ASIL-D readiness, high-end servers, microcontrollers, EU sovereignty, and ten-year silicon TCO. It is the synthesis we hand a client when the conversation starts with which architecture to pick for the next platform, and it sets the scene without replacing a dedicated comparative study.

Computex 2026 (June 2 to 5): what to watch

Computex 2026 is the Taipei trade show where SoC vendors, distros, and system integrators reveal their twelve-month roadmaps; for the open ISA it is the inflection event of the year because RVA23 silicon, VME-ready cores, and the Tenstorrent Ascalon-X timeline all converge on the same stage. The announcements below are the ones we recommend tracking closely.

Computex Taipei runs from June 2 to 5, 2026, on the theme "AI Together". This is the show where the hardware industry announces its cards for the next twelve months. Several announcements are expected:

• SiFive: next-gen P-series cores (P870 or successor), focus on performance per watt and NPU integration.
• Andes Technology: middle-range AndesCore extension and first VME-ready core demos.
• NVIDIA: confirmation or denial of open-core usage for the internal microcontrollers of upcoming GPUs (rumour persistent across several product cycles).
• Tenstorrent: Ascalon-X roadmap and possible additional RTL open-sourcing.
• ESWIN, StarFive, Telink, GigaDevice: SoCs for smartphone (StarFive JH7110 successor), TV (ESWIN W8), wearables (Telink), and industrial MCU (GigaDevice GD32V).
• Distros: Canonical, Red Hat, SUSE expected to detail their production support.

Our advice for design houses and integrators: if a platform review is scheduled for Q3 2026 or Q4 2026, waiting for Computex output before locking the SoC is rational. The roadmap deltas announced in Taipei in 2026 are significant enough that a choice locked three months before Computex risks being obsolete by time-to-market.

Bottom line

In 2026, RVA23 makes the architecture interoperable at distro scale, VME closes the AI gap, automotive moves to RFP, and the toolchain reaches production maturity. For high-performance servers, ARM stays the default bet until Ascalon-X actually ships.

Five takeaways from our evaluation engagements in 2025 and 2026, condensed into the points we hand a CTO or platform architect when the decision window is short:

• RVA23 is the inflection profile: it is the version that makes the architecture interoperable at distro scale, the equivalent of what the move to ARMv8 was for the ARM ecosystem.
• VME closes the AI gap: the Vector-Matrix Extension brings native outer-product instructions, reaching performance-per-watt parity with Apple AMX and ARM SME for edge inference.
• Automotive is moving from RFC to RFP: ASIL-D cores are now available at Andes, SiFive, Codasip and Infineon; the Cyber Resilience Act adds a sovereignty argument from end of 2027.
• The toolchain is production-ready: GCC v14, LLVM v18, mainline Linux 6.10+, Zephyr and FreeRTOS all support RVA23; Yocto remains the only per-SoC catch-up area.
• Lock the SoC after Computex 2026: if your platform review falls in Q3 or Q4 2026, waiting for the June Computex announcements before committing to a SoC family is the rational move.

FAQ

This FAQ gathers the five questions engineering teams ask us most often during a pre-study: the royalty-free model, the smartphone timeline, the role of the RVA23 profile, production readiness for industrial work, and which toolchain to pick. The answers condense our field experience.

Is RISC-V really royalty-free?

The instruction set is specified under a free licence by RISC-V International, with no royalties or per-seat licences. Concrete RTL implementations (the cores) are sold under various licences: some are open source (Rocket Chip, BOOM, Ascalon Apache 2.0), others are commercial products (SiFive Performance series, Andes AndesCore, Codasip Bk). The royalty-free model covers the ISA, not necessarily the silicon you integrate.

Can the open ISA replace ARM in smartphones?

Not before 2027-2028 in the high end. The Android software stack (HAL, modems, GPU drivers, Widevine DRM) is currently ARM-centric, and the transition would require a coordinated Google + OEM effort. On feature phones, smartwatches and IoT wearables, the architecture is already a reality (Amazfit T-Rex 3 Pro, Telink). The smartphone segment where the swing arrives first is Chinese mid-range, without Play Store constraints.

What is RVA23 and why does it matter?

RVA23 is a platform profile that standardises the mandatory hardware extensions to run Linux and FreeBSD at distro scale. It makes SoCs interoperable: a kernel signed for the profile boots on every compliant SoC, with no rebuild. Before it, every SoC was a special case. After, the industry can ship. This is the equivalent of what the move to ARMv8 was for the ARM ecosystem: the version that triggers industrial adoption.

Is RISC-V ready for production industrial projects?

Yes for MCU, IoT sensors, edge AI accelerators, and automotive ASIL-D (certified cores available at Andes, SiFive, Codasip, Infineon). More cautious for high-performance cloud servers where ARM Neoverse and AMD EPYC remain references until Ascalon-X actually ships. It is a defensible choice for any project finalising after Q3 2026, on a family with a published five-year roadmap.

What toolchain and IDE for RISC-V development?

The GCC and LLVM toolchains are mature (RVA23 and vector v1.0 supported in both). Professional IDEs (SEGGER Embedded Studio, IAR, Eclipse CDT, VS Code with PlatformIO) now ship native, stabilised support. Zephyr and FreeRTOS have stable ports. For debugging, OpenOCD covers the main probes (J-Link, FT2232, dedicated debuggers). It is now a mature professional development environment, not a research project.

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